ROM_CTRL/32KB Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.360s	7.729ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.720s	9.467ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.730s	2.030ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.020s	1.860ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.220s	1.960ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.840s	8.104ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.730s	2.030ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.220s	1.960ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.690s	7.609ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.730s	4.459ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.800s	8.542ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.332m	9.878ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.870s	15.009ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.510s	2.100ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.450s	2.176ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.450s	2.176ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.720s	9.467ms	5	5	100.00
		rom_ctrl_csr_rw	15.730s	2.030ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.220s	1.960ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.310s	2.211ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.720s	9.467ms	5	5	100.00
		rom_ctrl_csr_rw	15.730s	2.030ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.220s	1.960ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.310s	2.211ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.288m	115.863ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.828m	2.144ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.277m	2.089ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.828m	2.144ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.828m	2.144ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.828m	2.144ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.360s	7.729ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.360s	7.729ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.360s	7.729ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.277m	2.089ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.870s	15.009ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.828m	35.400ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.288m	115.863ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.828m	2.144ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.331h	96.261ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.56	97.67	100.00	98.97	97.45	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 35 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.113797083916997774558128694411236616727769244982418612273950816877385863763231
      Line 470, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121157168989 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 121157168989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.87600890189015287960395352949717742361590512513452884873618463719966418505335
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1037425644 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1037425644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 33 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 6.rom_ctrl_stress_all_with_rand_reset.15587682322119948139985957847520155227549358467034243565613316911469381094069
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d0fad9ee-f81b-42a8-ac09-df694905fc16
      

    • 20.rom_ctrl_stress_all_with_rand_reset.79907817171010492497776563986534786325954346283506203240736589343538529811198
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:ba8eaf7f-e229-4791-9bac-b89723647b0c
      

    • ... and 3 more failures.

Past Results

• Latest
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• 2024.06.12_04.56.54
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