ROM_CTRL/32KB Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.530s	8.398ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.040s	1.911ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.160s	13.926ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.790s	6.528ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.750s	1.787ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.750s	8.494ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.160s	13.926ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.750s	1.787ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.000s	9.519ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.320s	4.342ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.940s	12.960ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.720m	39.507ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.340s	4.062ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.590s	1.983ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.330s	2.052ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.330s	2.052ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.040s	1.911ms	5	5	100.00
		rom_ctrl_csr_rw	17.160s	13.926ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.750s	1.787ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.620s	5.273ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.040s	1.911ms	5	5	100.00
		rom_ctrl_csr_rw	17.160s	13.926ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.750s	1.787ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.620s	5.273ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.640m	56.039ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.744m	3.102ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.261m	5.766ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.744m	3.102ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.744m	3.102ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.744m	3.102ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.530s	8.398ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.530s	8.398ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.530s	8.398ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.261m	5.766ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.340s	4.062ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.953m	58.037ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.640m	56.039ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.744m	3.102ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.972h	62.619ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.67	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 20 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.60182611635953137346564646556403562728109051533845988286874199953653842712033
    Line 271, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 766535601 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 766535601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.69824929844642613037090833702265893012397086043347781221410970958830956262046
    Line 400, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19143306205 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19143306205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.11463714741319148179536536170557110739534337474046907049145068117004954179511
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8ffa1e0a-b9e8-4ffa-b505-47113eee53c9
```
  - 7.rom_ctrl_stress_all_with_rand_reset.105304794358707876558850917502650987432068679262333894979306375321781718643889
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bfff550a-e88b-44a2-b39b-cd5f671b0028
```
  - ... and 9 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.rom_ctrl_stress_all_with_rand_reset.18922854321685978572403633914820143420519768290643735143327619403168199537262
    Line 329, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69501499729 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 69501499729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.rom_ctrl_stress_all_with_rand_reset.26603266365958842207922435742581345831922912937656240071044919483685285739382
    Line 308, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 63440194068 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd6505e21
  UVM_INFO @ 63440194068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3fd3528c8c`