ROM_CTRL/32KB Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.500s	8.518ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.200s	5.892ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.820s	4.340ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.570s	2.200ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.630s	8.534ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.880s	14.051ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.820s	4.340ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.630s	8.534ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.470s	6.791ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.030s	5.209ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.030s	2.083ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.626m	13.698ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.900s	47.321ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.630s	15.108ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.980s	2.091ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.980s	2.091ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.200s	5.892ms	5	5	100.00
		rom_ctrl_csr_rw	16.820s	4.340ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.630s	8.534ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.830s	8.565ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.200s	5.892ms	5	5	100.00
		rom_ctrl_csr_rw	16.820s	4.340ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.630s	8.534ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.830s	8.565ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.679m	53.287ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.762m	1.876ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.320m	5.102ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.762m	1.876ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.762m	1.876ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.762m	1.876ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.500s	8.518ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.500s	8.518ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.500s	8.518ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.320m	5.102ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.900s	47.321ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.252m	160.632ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.679m	53.287ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.762m	1.876ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.575h	30.240ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.56	97.67	100.00	98.97	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.22010476282667888541874742060350553348434248309291010797170871289728813130817
    Line 337, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9674133952 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9674133952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.20809636323595030596479164711966492434909124293293362493848006343952877381685
    Line 375, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10274178353 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10274178353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.14842133257267690591336174934809088700147724995731880507001925467258811254670
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:22abf28f-bbc1-4cf9-a248-33736225049f
```
  - 17.rom_ctrl_stress_all_with_rand_reset.103967703786003118374930607821599321961796922961805389532218739156299186243845
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2d4b208c-9e8d-4271-bc6a-927179b7b98a
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.12127598488350818373488733310823212332903090840490380740139216507481221300187
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10007759681 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3e43188
  UVM_INFO @ 10007759681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.47282792873513862160322319690472422624916271287976789780019012608790353397846
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12465635198 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7ebc00b1
  UVM_INFO @ 12465635198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 28.rom_ctrl_stress_all.91942518166688573196844512317503807668866547360943668459103408346261360326761
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40148591826 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf38d9beb
  UVM_INFO @ 40148591826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be1c4a4f52`