ROM_CTRL/32KB Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.890s	7.862ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.840s	7.712ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.420s	8.578ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.090s	3.389ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.310s	4.263ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.430s	4.202ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.420s	8.578ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	4.263ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.610s	16.422ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.650s	22.753ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.170s	9.203ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.467m	197.161ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.380s	55.973ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.470s	7.425ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.210s	8.832ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.210s	8.832ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.840s	7.712ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	8.578ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	4.263ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.310s	7.665ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.840s	7.712ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	8.578ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	4.263ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.310s	7.665ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.716m	91.767ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.868m	8.819ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.278m	1.764ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.868m	8.819ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.868m	8.819ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.868m	8.819ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.890s	7.862ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.890s	7.862ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.890s	7.862ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.278m	1.764ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.380s	55.973ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.778m	483.154ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.716m	91.767ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.868m	8.819ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.455h	77.268ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	96.89	92.56	97.67	100.00	98.97	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.100409200034784290978064062804157170005902257220564892209944296730654373654966
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 873110024 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 873110024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.23091825119883747896811446192635111158417244261353666488038644158156963312103
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1776884218 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1776884218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.73287859630194527437855110229980169727661604499025657958800408696379067330485
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:16633a50-6ac6-4a97-aa8c-fc8ff7c9e8bd
```
  - 8.rom_ctrl_stress_all_with_rand_reset.14485702461769983384579754828680013857729506968441792583757854366600189255635
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:474dd370-b32c-49db-9e89-78577a929e0f
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 29.rom_ctrl_stress_all_with_rand_reset.99777735414084621303545106802459177743128256239753409229788258155672018450408
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11343936066 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb47b5c37
  UVM_INFO @ 11343936066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8db2a18db1`