3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 44.660s | 9.114ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 15.280s | 1.622ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 16.460s | 10.973ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.840s | 3.928ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 11.230s | 5.106ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 17.140s | 2.131ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 16.460s | 10.973ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 11.230s | 5.106ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 15.880s | 8.340ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 14.750s | 7.008ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.700s | 4.181ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.107m | 11.616ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.610s | 8.833ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 17.240s | 4.393ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 21.370s | 2.115ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 21.370s | 2.115ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 15.280s | 1.622ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.460s | 10.973ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 11.230s | 5.106ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 16.510s | 3.584ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 15.280s | 1.622ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.460s | 10.973ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 11.230s | 5.106ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 16.510s | 3.584ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.605m | 12.067ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.800m | 22.587ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.346m | 2.493ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.800m | 22.587ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.800m | 22.587ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.800m | 22.587ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 44.660s | 9.114ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 44.660s | 9.114ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 44.660s | 9.114ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.346m | 2.493ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 34.610s | 8.833ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 7.650m | 202.244ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.605m | 12.067ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.800m | 22.587ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.320h | 161.638ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 462 | 500 | 92.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.29 | 96.89 | 91.99 | 97.67 | 100.00 | 98.62 | 97.45 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
0.rom_ctrl_stress_all_with_rand_reset.30726474183191487510315339636850760607031949055746893922061875367118622075557
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 456285319 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 456285319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.88713683145031333862763862221471626024163805445323773169116893764384175480835
Line 360, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57852120665 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 57852120665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
4.rom_ctrl_stress_all_with_rand_reset.106908661334244452817088059656928914195557334064564363974117126898666470557738
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b85b4b68-d9cf-4315-b15e-7c80121b7e6c
12.rom_ctrl_stress_all_with_rand_reset.100994609767682263863271792869731724839929044724200231212913376029805728790240
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b2ef2385-d0ef-4add-b526-63a20c800066
... and 10 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
2.rom_ctrl_stress_all_with_rand_reset.48149761265978309805395025770461910420027220636500236249397592502602302083312
Line 332, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 87816534363 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x94e02ae3
UVM_INFO @ 87816534363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rom_ctrl_stress_all_with_rand_reset.17925048409211747483546192663171724363599643090664064691573840529581416505598
Line 282, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 54373962653 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x120f0ea6
UVM_INFO @ 54373962653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
27.rom_ctrl_stress_all_with_rand_reset.15953640421203196991758963492202736478490141529503565250084290082870764081488
Line 568, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 437476592949 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 437476592949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---