ROM_CTRL/32KB Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.050s	7.000ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.350s	7.680ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.150s	7.167ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.760s	2.127ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.620s	7.000ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.020s	2.243ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.150s	7.167ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.620s	7.000ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	17.340s	4.345ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.640s	8.059ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.420s	8.534ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.900m	38.586ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.540s	17.777ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.650s	2.155ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.860s	7.796ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.860s	7.796ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.350s	7.680ms	5	5	100.00
		rom_ctrl_csr_rw	16.150s	7.167ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.620s	7.000ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.680s	2.171ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.350s	7.680ms	5	5	100.00
		rom_ctrl_csr_rw	16.150s	7.167ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.620s	7.000ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.680s	2.171ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.636m	25.574ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.780m	6.344ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.338m	8.354ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.780m	6.344ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.780m	6.344ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.780m	6.344ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.050s	7.000ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.050s	7.000ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.050s	7.000ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.338m	8.354ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.540s	17.777ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.282m	112.708ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.636m	25.574ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.780m	6.344ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.837h	167.252ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			465	500	93.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.13	97.67	100.00	98.62	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.84672172457693334725006871895702437898926446816753549729249870562734760642983
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 677241641 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 677241641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.12470310768202393590634817092652818368252507671615010350617544623194661622147
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 620904291 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 620904291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.15521348357621612301618239626837765026961012748232410676998334957631512084123
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:13527c96-cbdd-44fd-9571-1215993a3e94
```
  - 20.rom_ctrl_stress_all_with_rand_reset.113657868402019432625998185114482975731262257592478099304699831104009532479398
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f8e6bf10-a320-49e4-b787-8682150ab72d
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.71404989262664784642476787945840736133453835585439898647332278516980124065117
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10030038565 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x14082c9f
  UVM_INFO @ 10030038565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b33f0bcb4a`