ROM_CTRL/32KB Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.520s	4.041ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.220s	1.562ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.520s	37.554ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.250s	1.896ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	18.140s	32.563ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.450s	9.377ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.520s	37.554ms	20	20	100.00
		rom_ctrl_csr_aliasing	18.140s	32.563ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.830s	5.290ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.880s	6.718ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.660s	9.344ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.803m	9.910ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	36.520s	4.286ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.980s	4.371ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.160s	8.523ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.160s	8.523ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.220s	1.562ms	5	5	100.00
		rom_ctrl_csr_rw	15.520s	37.554ms	20	20	100.00
		rom_ctrl_csr_aliasing	18.140s	32.563ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.870s	7.493ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.220s	1.562ms	5	5	100.00
		rom_ctrl_csr_rw	15.520s	37.554ms	20	20	100.00
		rom_ctrl_csr_aliasing	18.140s	32.563ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.870s	7.493ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.674m	45.705ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.785m	7.223ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.321m	9.129ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.785m	7.223ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.785m	7.223ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.785m	7.223ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.520s	4.041ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.520s	4.041ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.520s	4.041ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.321m	9.129ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
		rom_ctrl_kmac_err_chk	36.520s	4.286ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.506m	62.903ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.674m	45.705ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.785m	7.223ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.313h	101.592ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	96.89	92.42	97.67	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.107142282772582318504963747274720936066861679935859301820645192906077041992849
    Line 332, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32335435142 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32335435142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.84124711666102132363796857915086690559648197761940223524073480934460270269894
    Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4316393835 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4316393835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.103931552912000756150513617690341113002875824623695526945699056316159099361895
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:98ca73e6-deb5-4053-baf7-090632875568
```
  - 13.rom_ctrl_stress_all_with_rand_reset.70993193337244497819110454412888301280427448969094843669474765746454277034444
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:49117503-4185-4d1a-bc60-db35b69931bb
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.10478650634951352793376708890227311879355833496598031727650790727548701442335
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10011584567 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3e528475
  UVM_INFO @ 10011584567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.67390731088472833259880431347738156983363490112237338756743731271777779661779
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012906280 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x353e48fc
  UVM_INFO @ 10012906280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 6.rom_ctrl_tl_errors.6151237174156421691217692205388723211894464075747447616494913943081624724866
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1382542313 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1382542313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 16.rom_ctrl_kmac_err_chk.43875566022541622726344819376402063447837104630793206934705110179269063313329
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2758790897 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2758790897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb56ef55d0`