ROM_CTRL/32KB Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.930s	8.225ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.690s	2.420ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.610s	41.770ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.840s	1.847ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.270s	4.011ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.080s	9.248ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.610s	41.770ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.270s	4.011ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	17.270s	2.129ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.340s	5.545ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.470s	2.161ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.037m	77.819ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.790s	31.776ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.020s	8.625ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.780s	15.850ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.780s	15.850ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.690s	2.420ms	5	5	100.00
		rom_ctrl_csr_rw	16.610s	41.770ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.270s	4.011ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.620s	1.931ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.690s	2.420ms	5	5	100.00
		rom_ctrl_csr_rw	16.610s	41.770ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.270s	4.011ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.620s	1.931ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.733m	57.316ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.791m	1.870ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.321m	2.193ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.791m	1.870ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.791m	1.870ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.791m	1.870ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.930s	8.225ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.930s	8.225ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.930s	8.225ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.321m	2.193ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.790s	31.776ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.863m	65.645ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.733m	57.316ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.791m	1.870ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.275h	141.340ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	96.89	92.42	97.67	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.47160666229368292526478323943379655404708615945369025394125374655581364887018
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2170262977 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2170262977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.94306337259394998454441725701961571445308738594785359462637552714417248173290
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2014006961 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2014006961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.54795361514901721342886909173875915739986557604078188182394971672967008133637
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bbad08d2-2c65-4af7-9ece-aaaec1e9c841
```
  - 2.rom_ctrl_stress_all_with_rand_reset.50211252737221748650729266112740684399886762167754486598875934128666820373251
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:889c8e9a-5f53-48ee-bfd2-409c40b62c6a
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.85837983210969975519879519583899374211917367759779654490244226336852064160212
    Line 644, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 324609427719 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2be556d
  UVM_INFO @ 324609427719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.90692947054324960974277084619036401051526424083644639240804881996032859146227
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11216612535 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2b7fd519
  UVM_INFO @ 11216612535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e439226b6c`