ROM_CTRL/32KB Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	45.860s	8.179ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.880s	3.504ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.590s	4.297ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.940s	2.041ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.730s	1.248ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.600s	7.361ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.590s	4.297ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.730s	1.248ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.240s	7.469ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.610s	2.099ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.530s	2.134ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.759m	11.714ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.760s	10.832ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	17.140s	2.163ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.710s	4.474ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.710s	4.474ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.880s	3.504ms	5	5	100.00
		rom_ctrl_csr_rw	16.590s	4.297ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.730s	1.248ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.080s	33.901ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.880s	3.504ms	5	5	100.00
		rom_ctrl_csr_rw	16.590s	4.297ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.730s	1.248ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.080s	33.901ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.631m	12.085ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.735m	9.884ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.321m	9.582ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.735m	9.884ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.735m	9.884ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.735m	9.884ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	45.860s	8.179ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	45.860s	8.179ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	45.860s	8.179ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.321m	9.582ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.760s	10.832ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.299m	49.527ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.631m	12.085ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.735m	9.884ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.973h	138.929ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.67	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.68069646504445562206163986099958837141313248426936739359586670566989975285092
    Line 597, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87648365362 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87648365362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.1406099576145259077436278889700411498691019485070122125622707051400684069923
    Line 385, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14212784746 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14212784746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.102354243999230645333319858112055406666551433839534884297490200897085069540194
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:de312b88-9035-4ded-b449-63a9c333f9cd
```
  - 13.rom_ctrl_stress_all_with_rand_reset.7975818655387288272458059901753559752928614560796338322433254709810530041492
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:17bbed4c-eaef-4013-b05a-fc85a19b3b91
```
  - ... and 8 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 31.rom_ctrl_stress_all.70989687640196606310564530185065872183160557063226667882991553455832726864475
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 49675420774 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 49675420774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.rom_ctrl_stress_all_with_rand_reset.37362347732549054270684410800551601201679335451499847259413191096553393579882
    Line 732, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 945972203870 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 945972203870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 48.rom_ctrl_kmac_err_chk.106245482503510155824400162477725552936034222204195545569453313277810535717120
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3316455523 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3316455523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 30.rom_ctrl_stress_all_with_rand_reset.19023763812981813122202382695592652336771180959097795891600510996532682738860
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11792834382 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfaaed296
  UVM_INFO @ 11792834382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.715292734461521731080714870182382642535190022191884813129405447908379328057
    Line 322, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 113722712195 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xaa12916f
  UVM_INFO @ 113722712195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`