ROM_CTRL/32KB Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.360s	8.068ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.330s	2.792ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.620s	8.724ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.230s	25.230ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.540s	7.516ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.200s	5.183ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.620s	8.724ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.540s	7.516ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.300s	1.563ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.150s	17.244ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.570s	8.880ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.625m	69.622ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.390s	17.190ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.680s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.280s	2.017ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.280s	2.017ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.330s	2.792ms	5	5	100.00
		rom_ctrl_csr_rw	16.620s	8.724ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.540s	7.516ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.450s	2.163ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.330s	2.792ms	5	5	100.00
		rom_ctrl_csr_rw	16.620s	8.724ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.540s	7.516ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.450s	2.163ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.637m	21.600ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.899m	5.821ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.307m	2.047ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.899m	5.821ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.899m	5.821ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.899m	5.821ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.360s	8.068ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.360s	8.068ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.360s	8.068ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.307m	2.047ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.390s	17.190ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.251m	46.086ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.637m	21.600ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.899m	5.821ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.904h	35.547ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	96.89	92.28	97.67	100.00	98.62	97.30	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.49924472817720851023190007913956768988084486123996252203722897126528073214011
    Line 338, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56611957942 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56611957942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.99645178180135631239979714001213422934651415826470243890780276010579456820060
    Line 442, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20880555382 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20880555382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.26167135354693997156041304600648019343584068666650838473618156816096158898764
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ad685081-dac1-40ec-a1fa-d6cb180e877d
```
  - 1.rom_ctrl_stress_all_with_rand_reset.34736472315897308448879710504800225473199280099000783694890888009509933260634
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ba162ecb-2caf-4337-906a-0c893e53225d
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.63210714871489419907589814292123180379310371649321831163135584186159648848847
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10892728082 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xaffc209b
  UVM_INFO @ 10892728082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`