974aaab627| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 44.650s | 15.756ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 16.220s | 3.933ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 15.670s | 8.433ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 16.160s | 8.766ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 14.250s | 6.710ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 15.810s | 3.868ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 15.670s | 8.433ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 14.250s | 6.710ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 14.770s | 24.222ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 17.260s | 2.188ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.710s | 8.954ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.950m | 11.688ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.190s | 83.761ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.940s | 25.906ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 19.090s | 3.863ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 19.090s | 3.863ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 16.220s | 3.933ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.670s | 8.433ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 14.250s | 6.710ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.930s | 15.139ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 16.220s | 3.933ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.670s | 8.433ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 14.250s | 6.710ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.930s | 15.139ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.657m | 12.925ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.028m | 7.218ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.309m | 2.323ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.028m | 7.218ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.028m | 7.218ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.028m | 7.218ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 44.650s | 15.756ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 44.650s | 15.756ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 44.650s | 15.756ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.309m | 2.323ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 34.190s | 83.761ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.367m | 213.612ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.657m | 12.925ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.028m | 7.218ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.584h | 298.418ms | 20 | 50 | 40.00 |
| V3 | TOTAL | 20 | 50 | 40.00 | |||
| TOTAL | 470 | 500 | 94.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.31 | 96.89 | 91.99 | 97.67 | 100.00 | 98.28 | 97.30 | 99.07 |
UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
2.rom_ctrl_stress_all_with_rand_reset.86369269496014002425332400673661241454321026454436608176179924664300391272672
Line 480, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29874412485 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29874412485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rom_ctrl_stress_all_with_rand_reset.65644432452516096493531178793334802653837911593267239277440929314196261523203
Line 377, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15158935567 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15158935567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
5.rom_ctrl_stress_all_with_rand_reset.71566693962348782822282062803249903050903910908002369868548266029569943364098
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f637c47b-7522-4619-a356-5689a6a1c541
12.rom_ctrl_stress_all_with_rand_reset.43200108945442084378724971184039207795875793338018697514410051875950272014341
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:591209af-5b35-44c0-8456-5c5a7284d910
... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
8.rom_ctrl_stress_all_with_rand_reset.81022216579641425227700688068154082202245244487191479837095949333634039298595
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10006653764 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x87c044ce
UVM_INFO @ 10006653764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rom_ctrl_stress_all_with_rand_reset.85913051723876864707163140732151580543298470078124139502800586008264696648218
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10013977775 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xdb17f019
UVM_INFO @ 10013977775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.