ROM_CTRL/32KB Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.830s	16.970ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.820s	3.367ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.040s	2.191ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.930s	13.292ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.050s	7.467ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.550s	13.422ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.040s	2.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.050s	7.467ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.170s	4.026ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.190s	6.972ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.930s	8.279ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.130m	20.527ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.460s	13.129ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.130s	4.350ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.430s	9.473ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.430s	9.473ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.820s	3.367ms	5	5	100.00
		rom_ctrl_csr_rw	17.040s	2.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.050s	7.467ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.990s	2.114ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.820s	3.367ms	5	5	100.00
		rom_ctrl_csr_rw	17.040s	2.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.050s	7.467ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.990s	2.114ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.579m	48.243ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.782m	1.111ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.308m	13.916ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.782m	1.111ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.782m	1.111ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.782m	1.111ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.830s	16.970ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.830s	16.970ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.830s	16.970ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.308m	13.916ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.460s	13.129ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.665m	239.373ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.579m	48.243ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.782m	1.111ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.559h	235.866ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	96.89	91.99	97.67	100.00	98.28	97.30	98.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 18 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.95239778321016691085635515975423519332692716083965777694907703270744531298301
      Line 324, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9614842631 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9614842631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.rom_ctrl_stress_all_with_rand_reset.27629890329780990502701340186560529468142928600043008354179601750236334492610
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4538605366 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4538605366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 10 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.45991121611426666413070113552108289825479648359941504350141148456459747552003
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8aebdbeb-cd95-4768-9e60-c52eb6477a24
      

    • 12.rom_ctrl_stress_all_with_rand_reset.115107734827234372040775121171788833517441246168424475191995781424677552947489
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:85d3c0e1-6255-40c6-bea2-6f57a7de5ae5
      

    • ... and 8 more failures.

• UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 9.rom_ctrl_stress_all_with_rand_reset.48985780276388006065621369391075140450270059483528544943286277647477692439820
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11149762967 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe4cf1143
        UVM_INFO @ 11149762967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.rom_ctrl_stress_all_with_rand_reset.80618518125755120927142729030506993640491132226119553672528835346178197874043
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12388123730 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfde9f07c
        UVM_INFO @ 12388123730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.46432693459708173746474880206932094689192673558527155264953305057192001166598
      Line 690, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 830319269730 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 830319269730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.22_08.51.18
• 2024.07.21_08.31.48
• 2024.07.20_09.55.26
• 2024.07.19_08.56.30
• 2024.07.18_09.28.13
• 2024.07.17_09.39.36
• 2024.07.16_09.47.18