ROM_CTRL/32KB Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.290s	13.471ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.380s	5.611ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.420s	2.130ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.210s	1.515ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.340s	6.703ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.920s	8.160ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.420s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.340s	6.703ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.150s	1.423ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.850s	5.929ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.110s	4.751ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.808m	11.074ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.990s	34.620ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.550s	11.800ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.550s	2.071ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.550s	2.071ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.380s	5.611ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.340s	6.703ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.990s	14.779ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.380s	5.611ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.340s	6.703ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.990s	14.779ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.706m	13.186ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.810m	11.506ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.308m	12.424ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.810m	11.506ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.810m	11.506ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.810m	11.506ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.290s	13.471ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.290s	13.471ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.290s	13.471ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.308m	12.424ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.990s	34.620ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.871m	57.013ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.706m	13.186ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.810m	11.506ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.083h	44.993ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			466	500	93.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	96.89	91.99	97.67	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.62399464229286453689536459558914793143740621868970180182391342857923947364731
    Line 471, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25506898654 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25506898654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.6261721678605246925746647563673152992126712950449749222142488693394592677133
    Line 451, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49350409654 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49350409654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.51418445246515872055613728351904239335662318878819818459820614528411472714649
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6306a8f8-bcf3-44cb-b54f-456a7cda7170
```
  - 9.rom_ctrl_stress_all_with_rand_reset.115733357545353467804151111288601403279280090000778270922059330496734483513408
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:eba6a1fc-8eb3-49d6-b1d0-07a416a30d4e
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.98278465175191590424635373624023763036722870264666647992983289454026924867800
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013712933 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x39e672d4
  UVM_INFO @ 10013712933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`