ROM_CTRL/32KB Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	16.790s	19.693ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.310s	139.700us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.510s	1.703ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.470s	130.502us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.070s	127.799us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.800s	1.867ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.510s	1.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	127.799us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.020s	132.855us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.150s	140.179us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.870s	504.172us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	37.660s	635.557us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.000s	2.097ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.820s	1.830ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.140s	511.782us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.140s	511.782us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.310s	139.700us	5	5	100.00
		rom_ctrl_csr_rw	7.510s	1.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	127.799us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.740s	1.039ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.310s	139.700us	5	5	100.00
		rom_ctrl_csr_rw	7.510s	1.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	127.799us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.740s	1.039ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	46.840s	13.603ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.712m	307.638us	5	5	100.00
		rom_ctrl_tl_intg_err	1.191m	326.467us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.712m	307.638us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.712m	307.638us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.712m	307.638us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	16.790s	19.693ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	16.790s	19.693ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	16.790s	19.693ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.191m	326.467us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
		rom_ctrl_kmac_err_chk	17.000s	2.097ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.519m	21.327ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	46.840s	13.603ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.712m	307.638us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.280h	37.863ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			478	500	95.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	96.89	91.99	97.67	100.00	98.28	97.45	98.83

Failure Buckets

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 18 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.111214299112444416401856802998891534606588341072156703667033964902547790801129
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:996c4be7-27ce-4c65-a62c-617a40106c55
      

    • 3.rom_ctrl_stress_all_with_rand_reset.109961754066607142312071937394547394993207869154617348040084839828432867958963
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7ffd4f2e-e364-4457-aaab-72f675596144
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.112502965430844702457781082846522509139723525979706967648781974206176314565660
      Line 332, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27807601356 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27807601356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.rom_ctrl_stress_all_with_rand_reset.86819026442207143696734628799524315366417897292592165372808894110994446640585
      Line 292, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3193606711 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3193606711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

Past Results

• Latest
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