ROM_CTRL/32KB Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.760s	1.002ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.530s	349.160us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.370s	1.968ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.500s	132.491us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.100s	131.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.560s	146.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.370s	1.968ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.100s	131.457us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.070s	132.965us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.050s	132.804us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.030s	987.815us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	40.380s	964.978us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.250s	1.968ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.560s	2.905ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.340s	675.538us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.340s	675.538us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.530s	349.160us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	1.968ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.100s	131.457us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.730s	2.094ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.530s	349.160us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	1.968ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.100s	131.457us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.730s	2.094ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	46.120s	13.013ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.703m	377.915us	5	5	100.00
		rom_ctrl_tl_intg_err	1.286m	1.146ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.703m	377.915us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.703m	377.915us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.703m	377.915us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.760s	1.002ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.760s	1.002ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.760s	1.002ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.286m	1.146ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.250s	1.968ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.518m	12.778ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	46.120s	13.013ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.703m	377.915us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.896h	27.445ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			481	500	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.67	100.00	98.28	97.30	98.37

Failure Buckets

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 14 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.2952520591679050079643111164766607018281935799442214875400855090924208876287
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1b8631b1-f145-4e38-9ab9-e4494d89636c
      

    • 6.rom_ctrl_stress_all_with_rand_reset.57279595711539396257375806872736943691368934228664635632060846370522175085066
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:563a9d32-1c03-4329-b324-0991bcb8fd20
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.33740710635603212426322726684231444556181928061752572534769938973973460475031
      Line 364, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10228120751 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10228120751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.rom_ctrl_stress_all_with_rand_reset.35268701485687669316748086353375037536044763306020847927695628360150229158976
      Line 453, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57668704595 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 57668704595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

Past Results

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