eca25c0ff8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 12.430s | 1.096ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.240s | 130.591us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 5.200s | 895.641us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.560s | 520.909us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.220s | 498.651us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 8.490s | 7.124ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 5.200s | 895.641us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.220s | 498.651us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 8.060s | 1.029ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 4.960s | 132.936us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 8.990s | 1.095ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 49.590s | 3.668ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 16.870s | 4.090ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 7.690s | 2.693ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 10.120s | 1.898ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 10.120s | 1.898ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.240s | 130.591us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.200s | 895.641us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.220s | 498.651us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.570s | 1.010ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.240s | 130.591us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.200s | 895.641us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.220s | 498.651us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.570s | 1.010ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 49.810s | 50.047ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.684m | 614.241us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.189m | 593.398us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.684m | 614.241us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.684m | 614.241us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.684m | 614.241us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 12.430s | 1.096ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 12.430s | 1.096ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 12.430s | 1.096ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.189m | 593.398us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 16.870s | 4.090ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.456m | 20.183ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 49.810s | 50.047ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.684m | 614.241us | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.974h | 72.545ms | 23 | 50 | 46.00 |
| V3 | TOTAL | 23 | 50 | 46.00 | |||
| TOTAL | 472 | 500 | 94.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.20 | 96.89 | 91.99 | 97.67 | 100.00 | 98.28 | 97.45 | 98.14 |
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
0.rom_ctrl_stress_all_with_rand_reset.26139600714173322651325369081779108083558806180973434206911186846985627841776
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e8eb5a46-9f5e-4fa1-bdbd-8233f83f0173
1.rom_ctrl_stress_all_with_rand_reset.1255819481419506039570420656979158645142568450974660525735807494208945739568
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e38f5b08-bef8-4559-a356-4868732257fe
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
16.rom_ctrl_stress_all_with_rand_reset.99731911424609336374644096714194499637856253357831397106133426157949929058874
Line 558, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 41116327361 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 41116327361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rom_ctrl_stress_all_with_rand_reset.21532572594628833773673970505671905856747792778550912498542129553640051917154
Line 318, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14171327419 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14171327419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
31.rom_ctrl_corrupt_sig_fatal_chk.5994074535557791056889026527760790449598081516747179718912067226493072303874
Line 303, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 37798800441 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 37798800441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---