ROM_CTRL/32KB Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.720s	2.023ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.290s	516.474us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.370s	500.860us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.440s	130.129us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.460s	1.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.390s	295.379us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.370s	500.860us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.009ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.100s	255.175us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.020s	519.135us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.750s	2.910ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	22.050s	1.031ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	15.920s	7.603ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.600s	1.025ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.570s	590.544us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.570s	590.544us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.290s	516.474us	5	5	100.00
		rom_ctrl_csr_rw	5.370s	500.860us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.009ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.430s	158.069us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.290s	516.474us	5	5	100.00
		rom_ctrl_csr_rw	5.370s	500.860us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.009ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.430s	158.069us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.380s	802.718us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.728m	645.789us	5	5	100.00
		rom_ctrl_tl_intg_err	1.462m	4.169ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.728m	645.789us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.728m	645.789us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.728m	645.789us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.720s	2.023ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.720s	2.023ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.720s	2.023ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.462m	4.169ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
		rom_ctrl_kmac_err_chk	15.920s	7.603ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.532m	24.984ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.380s	802.718us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.728m	645.789us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.781m	6.786ms	1	50	2.00
V3		TOTAL			1	50	2.00
		TOTAL			411	460	89.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.67	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.19053912746632936489576104928277324379210149469029029052781762979776771446144
    Line 314, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9305067976 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9305067976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.113757920470585319876467577387700992478588360798417916060313506719218086100630
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   9191739 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @   9191739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.87053995005917860679075043077128336304904472787569096586881494434758942247816
    Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2474880031 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2474880031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.57448289548249825199428369000093729242821276287032645953076608367713267400651
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106719058 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106719058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 15.rom_ctrl_stress_all_with_rand_reset.51432107238206174098886001324394495314596454433265584422848311976600880773766
    Line 301, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39914779992 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 39914779992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.95942895502338368920173676413913804128676308609201370745233226817477998680053
    Line 268, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4595540775 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4595540775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.71160416671681352772388789792671459143689370011295951958310962271509105741283
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1407564742 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1407564742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `584c3d46af`