ROM_CTRL/32KB Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.560s	537.206us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.240s	131.238us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.730s	510.241us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.530s	501.468us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.270s	518.855us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.260s	153.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.730s	510.241us	20	20	100.00
		rom_ctrl_csr_aliasing	5.270s	518.855us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.180s	226.078us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.190s	131.437us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.120s	1.050ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	27.010s	3.081ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.270s	2.061ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.370s	1.958ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.480s	155.463us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.480s	155.463us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.240s	131.238us	5	5	100.00
		rom_ctrl_csr_rw	7.730s	510.241us	20	20	100.00
		rom_ctrl_csr_aliasing	5.270s	518.855us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.120s	142.535us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.240s	131.238us	5	5	100.00
		rom_ctrl_csr_rw	7.730s	510.241us	20	20	100.00
		rom_ctrl_csr_aliasing	5.270s	518.855us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.120s	142.535us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.670s	797.586us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.731m	329.239us	5	5	100.00
		rom_ctrl_tl_intg_err	1.271m	651.650us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.731m	329.239us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.731m	329.239us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.731m	329.239us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.560s	537.206us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.560s	537.206us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.560s	537.206us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.271m	651.650us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.270s	2.061ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.260m	3.096ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.670s	797.586us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.731m	329.239us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.867h	24.299ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			432	460	93.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	96.89	92.42	97.67	100.00	98.62	97.45	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.3456321774098339286572759892307294114828784154445251004358171630570769696718
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3ba30e9b-e393-449c-9578-c4c98ba7741f
```
  - 4.rom_ctrl_stress_all_with_rand_reset.59089789792671650228608993116217598843493180856681063040406204289515553453286
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1f244907-d3c3-415b-bcba-03f9f97d131e
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.90407058350266077379214945011067105123657327219967411628952912733422376219862
    Line 347, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14299123892 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14299123892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.108182988187845105919684760154258305944648652623350769603155359756167444996692
    Line 434, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31880782098 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31880782098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.38982067354818197088890444370010124712594057667244701566225027409304997730427
    Line 349, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16440232423 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16440232423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.107927433525055451297922688487204154162607016954905347273645210416663207129308
    Line 463, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 31005863203 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 31005863203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.67691670862225863433396723318509818959965617381220904358119372977761197275471
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173163677 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 173163677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.rom_ctrl_stress_all_with_rand_reset.78307212710902273646327751915977157170598404583371968225173316377273619109695
    Line 477, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 390050246024 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 390050246024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.rom_ctrl_stress_all_with_rand_reset.45965031800703011704440572895880935530670529723728788096780319536469021130474
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1080458044 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1080458044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.rom_ctrl_stress_all_with_rand_reset.92547585264169588480844837412410542979230088583035746432786183417003552943867
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  90342779 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  90342779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.95895220781818443713859796071616146389109308691082151993391146980411657626513
    Line 482, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 299594364288 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 299594364288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3707c48f56`