c082b8981f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 6.620s | 270.867us | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.340s | 266.429us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 5.530s | 133.139us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.380s | 129.654us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.330s | 133.540us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 6.270s | 143.636us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 5.530s | 133.139us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.330s | 133.540us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 7.520s | 4.494ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.190s | 525.937us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 8.520s | 779.521us | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 35.290s | 2.014ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 16.540s | 4.473ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 7.750s | 1.068ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 10.160s | 289.037us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 10.160s | 289.037us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.340s | 266.429us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.530s | 133.139us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.330s | 133.540us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.040s | 266.215us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.340s | 266.429us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.530s | 133.139us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.330s | 133.540us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.040s | 266.215us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 48.170s | 19.894ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.774m | 1.272ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.177m | 631.038us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.774m | 1.272ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.774m | 1.272ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.774m | 1.272ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 6.620s | 270.867us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 6.620s | 270.867us | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 6.620s | 270.867us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.177m | 631.038us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 16.540s | 4.473ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 4.998m | 31.746ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 48.170s | 19.894ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.774m | 1.272ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 4.489m | 7.470ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| TOTAL | 412 | 460 | 89.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.19 | 96.89 | 91.85 | 97.67 | 100.00 | 98.28 | 97.30 | 98.37 |
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 30 failures:
0.rom_ctrl_stress_all_with_rand_reset.10377367659565803940922935307865736347829655066600463001112019116095846101747
Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12557186 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 12557186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_ctrl_stress_all_with_rand_reset.109349227998408866218850108221651810096227633455069712458852643371900328977397
Line 297, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1668735148 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1668735148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (cip_base_vseq.sv:848) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
6.rom_ctrl_stress_all_with_rand_reset.110667816444192166061661211066460357620974760014956755577130562486819670785431
Line 322, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2244946353 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2244946353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rom_ctrl_stress_all_with_rand_reset.25952430988211700025367570040159038781419985557404315140390895144457702166955
Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2585234362 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2585234362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
5.rom_ctrl_stress_all_with_rand_reset.15854365002341138196507094055559642217434358653933706182849949175826966168682
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90919210 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 90919210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rom_ctrl_stress_all_with_rand_reset.40027411309393338107325725048254493589356156293900044507653908389409487013731
Line 298, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1551340428 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1551340428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
12.rom_ctrl_stress_all_with_rand_reset.30276945867768174837398113511761106267882192695020732380597501205289026459488
Line 275, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1054085577 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1054085577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
36.rom_ctrl_corrupt_sig_fatal_chk.71053898537639275539832947361425367860524982319463948468412036081807117714134
Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 28112482802 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 28112482802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---