ROM_CTRL/32KB Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.570s	527.395us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.760s	267.656us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.150s	491.380us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.370s	498.571us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.070s	133.660us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.770s	524.577us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.150s	491.380us	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	133.660us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.060s	493.780us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.050s	524.433us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.030s	517.906us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	35.160s	4.139ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.680s	3.931ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.920s	508.642us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.280s	1.704ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.280s	1.704ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.760s	267.656us	5	5	100.00
		rom_ctrl_csr_rw	7.150s	491.380us	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	133.660us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.930s	134.743us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.760s	267.656us	5	5	100.00
		rom_ctrl_csr_rw	7.150s	491.380us	20	20	100.00
		rom_ctrl_csr_aliasing	5.070s	133.660us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.930s	134.743us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.280s	682.336us	8	20	40.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.659m	433.046us	5	5	100.00
		rom_ctrl_tl_intg_err	1.270m	798.685us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.659m	433.046us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.659m	433.046us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.659m	433.046us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.570s	527.395us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.570s	527.395us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.570s	527.395us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.270m	798.685us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
		rom_ctrl_kmac_err_chk	16.680s	3.931ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.489m	17.567ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.280s	682.336us	8	20	40.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.659m	433.046us	5	5	100.00
V2S		TOTAL			82	95	86.32
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.678h	81.377ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			423	460	91.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	96.89	92.42	97.67	100.00	98.62	97.30	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.38110205043396493595168700299002579476530141080838400427548694427199678852361
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:45af8ef6-ade8-44f3-a1ae-e633d4a90c96
```
  - 9.rom_ctrl_stress_all_with_rand_reset.52017868301678568251586071404457455700754518263075125842018919403696388118125
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:68a2595c-7b7b-44cf-9ebc-2a7200c2ea7e
```
  - ... and 8 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 9 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 9 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.4027924304614246339900882233807862849550028539332749366969173740184276382204
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1379405203 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 1379405203 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1379405203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_ctrl_passthru_mem_tl_intg_err.47312361956846686181888954671461600032978018391031491574736520006978063455606
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 352111297 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 352111297 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 352111297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.104767725649003902096495673528873731945613693658061743678774409594362611482419
    Line 268, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1605154901 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1605154901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.83487337981621178234105514953328775396176137127725901390386885419540045113505
    Line 337, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36822172212 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36822172212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.69604573581651688782069283738382192160139127940233149731276258734319142534242
    Line 502, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25807094605 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 25807094605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rom_ctrl_stress_all_with_rand_reset.26226196672077881387350686524613176146759190782939042907730192148090509235956
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 397885376 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 397885376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

5.rom_ctrl_passthru_mem_tl_intg_err.95796762214318940025975747026628337875725371185398840839204854377775642872098
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 127742265 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 127742265 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 127742265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.rom_ctrl_passthru_mem_tl_intg_err.6328979717289933544247238466643086450587241092017987353616145200313146786768
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2482222059 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 2482222059 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2482222059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.71420756126258342019333885281886365669627745824142039470912414070896046104990
    Line 355, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9547806941 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 9547806941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rom_ctrl_stress_all_with_rand_reset.73437044346795310232855970158265854160852564780896106636217698365831877422068
    Line 704, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 47650838479 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 47650838479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.98507889245018559576883653194867634764015496552781829130178265654068614281876
    Line 615, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43151923540 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 43151923540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.rom_ctrl_stress_all_with_rand_reset.22879932494097901851782149870683796853062192064342824914980176622190555215217
    Line 899, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72375782828 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 72375782828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 26.rom_ctrl_corrupt_sig_fatal_chk.96688025652781702726200402760621265966443624418097453615999190361923183290504
    Line 285, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 21300153726 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 21300153726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```