07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 6.600s | 545.387us | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.320s | 539.251us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 5.230s | 256.140us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.470s | 520.377us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 7.610s | 506.677us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 7.620s | 512.347us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 5.230s | 256.140us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 7.610s | 506.677us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 5.220s | 126.297us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.140s | 132.588us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 8.510s | 2.492ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 20.520s | 677.791us | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 16.590s | 2.339ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 5.320s | 131.556us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 10.960s | 174.493us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 10.960s | 174.493us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.320s | 539.251us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.230s | 256.140us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 7.610s | 506.677us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.990s | 140.539us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.320s | 539.251us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.230s | 256.140us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 7.610s | 506.677us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.990s | 140.539us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 32.980s | 3.264ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.875m | 861.348us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.188m | 665.352us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.875m | 861.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.875m | 861.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.875m | 861.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 6.600s | 545.387us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 6.600s | 545.387us | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 6.600s | 545.387us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.188m | 665.352us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 16.590s | 2.339ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 4.144m | 13.233ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 32.980s | 3.264ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.875m | 861.348us | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 1.982h | 29.935ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 428 | 460 | 93.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.21 | 96.89 | 91.99 | 97.67 | 100.00 | 98.28 | 97.30 | 98.37 |
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
0.rom_ctrl_stress_all_with_rand_reset.36499863666443896020526935968460371289542524286711000633679364906080601751520
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3ca3a897-b4f8-43a5-943c-d05c2785b2c5
3.rom_ctrl_stress_all_with_rand_reset.30877188965778711825305850271587185677626401883365468252586364334958308470905
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b047a9dd-998b-492c-a938-4b56b44aa5be
... and 19 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
4.rom_ctrl_stress_all_with_rand_reset.48853083086800278310836551396643695797435152179578470824923224723155936762527
Line 357, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16337181053 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16337181053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rom_ctrl_stress_all_with_rand_reset.44527513611118683960406090279174423185288381608057216090603184908617474255233
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 359371375 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 359371375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
18.rom_ctrl_stress_all_with_rand_reset.5913085138650213360254157612072674622591400429120038527794368113521087153176
Line 388, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9769065603 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9769065603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rom_ctrl_stress_all_with_rand_reset.111217244567930378190387164313088790127979167036127872988810833643371774434348
Line 398, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43892943855 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 43892943855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
24.rom_ctrl_stress_all_with_rand_reset.56959184009262481498567854883685409798150864516501493516680364860036666883173
Line 407, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 15179099864 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 15179099864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---