07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 6.530s | 137.036us | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.250s | 544.324us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 5.220s | 257.733us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 7.770s | 1.887ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.120s | 695.087us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 7.130s | 2.062ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 5.220s | 257.733us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.120s | 695.087us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 5.180s | 619.167us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.100s | 391.781us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 8.790s | 505.588us | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 23.660s | 392.402us | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 16.340s | 1.036ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 7.860s | 979.575us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 11.850s | 1.974ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 11.850s | 1.974ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.250s | 544.324us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.220s | 257.733us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.120s | 695.087us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 9.330s | 2.438ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.250s | 544.324us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 5.220s | 257.733us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.120s | 695.087us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 9.330s | 2.438ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 48.140s | 12.460ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.898m | 1.892ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.370m | 1.247ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.898m | 1.892ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.898m | 1.892ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.898m | 1.892ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 6.530s | 137.036us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 6.530s | 137.036us | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 6.530s | 137.036us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.370m | 1.247ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 16.340s | 1.036ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.520m | 6.906ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 48.140s | 12.460ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.898m | 1.892ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.820h | 83.639ms | 23 | 50 | 46.00 |
| V3 | TOTAL | 23 | 50 | 46.00 | |||
| TOTAL | 433 | 460 | 94.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.26 | 96.89 | 91.99 | 97.67 | 100.00 | 98.62 | 97.30 | 98.37 |
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
1.rom_ctrl_stress_all_with_rand_reset.10617012128639947777326360812478691548966956524806920899200672847807598270406
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d39e9077-94a0-4393-89ed-0b81e6726396
8.rom_ctrl_stress_all_with_rand_reset.96913269226913560475859068216869747099974684222270783955116338952427744980259
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f7a743af-9311-40f8-8843-ca77f2a6e922
... and 14 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 7 failures:
4.rom_ctrl_stress_all_with_rand_reset.53993041901561681632935406935381067485871756209473399595332170887261678430788
Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 130513974 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 130513974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rom_ctrl_stress_all_with_rand_reset.73434135078596376395493100265371339396380735628865030547916328417311695585944
Line 554, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26735266576 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 26735266576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
9.rom_ctrl_stress_all_with_rand_reset.1293991375239248491221020729994249981649068523613049209744270897060679797340
Line 269, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 622314469 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 622314469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rom_ctrl_stress_all_with_rand_reset.71281975049816558019139957589102603672502139695319864768521060863917732790440
Line 539, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37755958121 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 37755958121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.