ROM_CTRL/32KB Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.810s 1.920ms 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.930s 181.110us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 4.920s 127.189us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.180s 132.371us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.710s 833.318us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.230s 509.936us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.920s 127.189us 20 20 100.00
rom_ctrl_csr_aliasing 4.710s 833.318us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 4.870s 518.563us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.860s 256.221us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.600s 1.260ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 25.220s 1.067ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.720s 990.889us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 5.080s 497.223us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.760s 9.923ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.760s 9.923ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.930s 181.110us 5 5 100.00
rom_ctrl_csr_rw 4.920s 127.189us 20 20 100.00
rom_ctrl_csr_aliasing 4.710s 833.318us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.710s 1.035ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.930s 181.110us 5 5 100.00
rom_ctrl_csr_rw 4.920s 127.189us 20 20 100.00
rom_ctrl_csr_aliasing 4.710s 833.318us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.710s 1.035ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 31.600s 1.643ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.747m 850.861us 5 5 100.00
rom_ctrl_tl_intg_err 1.202m 409.661us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.747m 850.861us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.747m 850.861us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.747m 850.861us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.810s 1.920ms 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.810s 1.920ms 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.810s 1.920ms 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.202m 409.661us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
rom_ctrl_kmac_err_chk 14.720s 990.889us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 4.528m 63.596ms 49 50 98.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 31.600s 1.643ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.747m 850.861us 5 5 100.00
V2S TOTAL 94 95 98.95
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.652m 19.923ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 457 460 99.35

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 3 75.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.40 96.89 92.13 97.67 100.00 98.28 97.75 99.06

Failure Buckets

Past Results