ROM_CTRL/32KB Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.980s	503.329us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.580s	160.578us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.030s	131.531us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.150s	131.923us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.510s	688.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.620s	515.055us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.030s	131.531us	20	20	100.00
		rom_ctrl_csr_aliasing	6.510s	688.011us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.480s	509.783us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.750s	253.589us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.260s	569.575us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	23.770s	2.776ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.270s	999.606us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	6.930s	2.338ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.120s	154.306us	18	20	90.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.120s	154.306us	18	20	90.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.580s	160.578us	5	5	100.00
		rom_ctrl_csr_rw	5.030s	131.531us	20	20	100.00
		rom_ctrl_csr_aliasing	6.510s	688.011us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.720s	141.252us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.580s	160.578us	5	5	100.00
		rom_ctrl_csr_rw	5.030s	131.531us	20	20	100.00
		rom_ctrl_csr_aliasing	6.510s	688.011us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.720s	141.252us	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.690s	8.745ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.650m	848.633us	5	5	100.00
		rom_ctrl_tl_intg_err	1.316m	763.109us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.650m	848.633us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.650m	848.633us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.650m	848.633us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.980s	503.329us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.980s	503.329us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.980s	503.329us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.316m	763.109us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
		rom_ctrl_kmac_err_chk	11.270s	999.606us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.206m	121.128ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.690s	8.745ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.650m	848.633us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.775m	9.504ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			456	460	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	96.89	92.56	97.67	100.00	98.62	97.90	99.06

Failure Buckets

UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
- Test rom_ctrl_tl_errors has 2 failures.
  - 8.rom_ctrl_tl_errors.11360253321196013191222718691614597750286200336005015383837553404527025521251
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1376665129 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1376665129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_tl_errors.77879500118498955358164053600594906059930808323626505441273028003672585132106
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1380119556 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1380119556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.40114201629099071069676096362134957426243146195917204307617905147828410825948
    Line 364, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49554872546 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 49554872546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.69341167264046972017814150126478749095921565672664817095721637649183468840322
    Line 275, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 932007337 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 932007337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`