ROM_CTRL/32KB Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.340s	1.021ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.430s	96.310us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.900s	210.619us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.350s	340.137us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.120s	1.554ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.410s	1.046ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.900s	210.619us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	1.554ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.810s	521.441us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.580s	515.150us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.070s	1.798ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	22.300s	1.640ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	15.220s	1.037ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	6.890s	520.543us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.890s	2.042ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.890s	2.042ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.430s	96.310us	5	5	100.00
		rom_ctrl_csr_rw	4.900s	210.619us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	1.554ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.740s	140.870us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.430s	96.310us	5	5	100.00
		rom_ctrl_csr_rw	4.900s	210.619us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	1.554ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.740s	140.870us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.780s	1.647ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.669m	271.347us	5	5	100.00
		rom_ctrl_tl_intg_err	1.315m	765.522us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.669m	271.347us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.669m	271.347us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.669m	271.347us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.340s	1.021ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.340s	1.021ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.340s	1.021ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.315m	765.522us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
		rom_ctrl_kmac_err_chk	15.220s	1.037ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.749m	13.537ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.780s	1.647ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.669m	271.347us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.106m	22.031ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			453	460	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.13	97.67	100.00	98.28	98.05	98.83

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.81488921899176689804534469523945063125767124275052449937117123208194617761929
    Line 389, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9089102400 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 9089102400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rom_ctrl_stress_all_with_rand_reset.3777189414558246953362226219379108902465070871490748265045540513632308069169
    Line 295, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3999987261 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 3999987261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 7.rom_ctrl_kmac_err_chk.93563837505925373079168649479734650882908956095999736146722886175150044604774
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2766311628 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2766311628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`