ROM_CTRL/64KB Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.344m	15.467ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	39.470s	8.545ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.850s	3.944ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.170s	3.783ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	30.490s	14.756ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	30.830s	8.239ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.850s	3.944ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.490s	14.756ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.240s	7.343ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.560s	4.267ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.940s	6.933ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.132m	26.617ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.226m	36.992ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	35.580s	25.282ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	34.580s	15.583ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	34.580s	15.583ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	39.470s	8.545ms	5	5	100.00
		rom_ctrl_csr_rw	31.850s	3.944ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.490s	14.756ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.940s	19.932ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	39.470s	8.545ms	5	5	100.00
		rom_ctrl_csr_rw	31.850s	3.944ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.490s	14.756ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.940s	19.932ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.159m	172.168ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.111m	4.062ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.930m	21.986ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.111m	4.062ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.111m	4.062ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.111m	4.062ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.344m	15.467ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.344m	15.467ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.344m	15.467ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.930m	21.986ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.226m	36.992ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.233m	113.974ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.159m	172.168ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.111m	4.062ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.749h	79.032ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			453	500	90.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.56	96.97	93.15	97.88	100.00	98.69	97.88	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 33 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.11783011211434433632665057072541428439926835006213986197488384685728472495828
    Line 335, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7792744035 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7792744035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.85380210458911057795853519074467771448459101053607051073172724311974649188173
    Line 423, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29362091311 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29362091311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.77651506973703933415741551951942404222000850745764668548399457292681779179951
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10505467265 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcf3efa48
  UVM_INFO @ 10505467265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rom_ctrl_stress_all_with_rand_reset.65401008983314384356518623084896470105185266439042733509056886995764574469724
    Line 449, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 459467946665 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x4c874f79
  UVM_INFO @ 459467946665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.69887005224965228976351579973248618423634862627375097349076175603837818803703
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:77507230-4cd5-4c83-9e41-9ce494737070
```
  - 5.rom_ctrl_stress_all_with_rand_reset.113574564482694814957332722163338946015645091419769111889225084777164943938620
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8fb47f19-3269-4bb4-b355-72b61040b7b3
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all has 2 failures.
  - 1.rom_ctrl_stress_all.61692830141047214263479050680208984581681944462464727314915838520940434504632
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40028286775 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf87725d5
  UVM_INFO @ 40028286775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.rom_ctrl_stress_all.96777793763522261058178504523860370142579905437317737423791834910739565004651
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40016691669 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x277712d4
  UVM_INFO @ 40016691669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_smoke has 1 failures.
  - 5.rom_ctrl_smoke.34075348651044402506288714499102347916949878358655737242017294141366312939221
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017663173 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe20edd48
  UVM_INFO @ 40017663173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d0c52cdadd`