ROM_CTRL/64KB Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.322m	33.555ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	27.430s	4.208ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.390s	8.191ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	25.010s	2.899ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.250s	14.274ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	30.380s	15.701ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.390s	8.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.250s	14.274ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	32.080s	4.112ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.250s	4.270ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.650s	52.832ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.046m	104.013ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.195m	16.437ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.880s	4.170ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	32.250s	12.106ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	32.250s	12.106ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	27.430s	4.208ms	5	5	100.00
		rom_ctrl_csr_rw	32.390s	8.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.250s	14.274ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.810s	4.158ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	27.430s	4.208ms	5	5	100.00
		rom_ctrl_csr_rw	32.390s	8.191ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.250s	14.274ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.810s	4.158ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.163m	37.424ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.696m	547.923us	5	5	100.00
		rom_ctrl_tl_intg_err	2.906m	8.746ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.696m	547.923us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.696m	547.923us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.696m	547.923us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.322m	33.555ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.322m	33.555ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.322m	33.555ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.906m	8.746ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.195m	16.437ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	17.048m	768.475ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.163m	37.424ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.696m	547.923us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.855h	132.488ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	92.13	97.72	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.63469579946865927027022617536197135242064209989211149920276794002924721079017
    Line 332, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13471135875 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13471135875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.104208487113390889443710972112157312503317261694265311917674595501550083918631
    Line 327, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10615241724 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10615241724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.92194140683092519918538150743432238272517905695659305091299760856793659227011
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d367eaf4-1acb-4cae-9b48-97362567a203
```
  - 11.rom_ctrl_stress_all_with_rand_reset.34250364816949108641932127193476341276373606554249079091390299552471498103714
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:16c53c11-fe1f-48d4-81d7-8ff843fd01a4
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.31127251743708076494769422264627061752486056329672069774614225721311744759024
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005682566 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x32c3a49a
  UVM_INFO @ 10005682566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.rom_ctrl_stress_all_with_rand_reset.60507051329213783525453385055680064568832096684639053694185001503318319547528
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005577803 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc4977b57
  UVM_INFO @ 10005577803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 12.rom_ctrl_smoke.107750389355927163119962801923816782102662798694476411823896577004441990514457
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017768121 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xd70fbdae
  UVM_INFO @ 40017768121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.rom_ctrl_smoke.94544383908542112969983286109695915345080463428324974872572809350150524461842
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40010755103 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xab3fc14a
  UVM_INFO @ 40010755103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 16.rom_ctrl_tl_errors.49726383374338185163637731387692701387710885623856677633860124200528962614647
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 2746025671 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2746025671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f92a5ee77b`