0e5093d709| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.510m | 16.126ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 38.780s | 34.320ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 33.320s | 17.346ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 18.630s | 24.509ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 26.860s | 13.222ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 32.830s | 4.447ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 33.320s | 17.346ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 26.860s | 13.222ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 32.190s | 11.238ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 32.010s | 4.174ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.380s | 4.206ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.673m | 47.405ms | 48 | 50 | 96.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.175m | 24.354ms | 48 | 50 | 96.00 |
| V2 | alert_test | rom_ctrl_alert_test | 32.830s | 68.525ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 38.230s | 17.776ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 38.230s | 17.776ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 38.780s | 34.320ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.320s | 17.346ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 26.860s | 13.222ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 30.910s | 15.755ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 38.780s | 34.320ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.320s | 17.346ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 26.860s | 13.222ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 30.910s | 15.755ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 236 | 240 | 98.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 2.934m | 67.780ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.253m | 17.277ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.904m | 8.001ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.253m | 17.277ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.253m | 17.277ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.253m | 17.277ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.510m | 16.126ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.510m | 16.126ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.510m | 16.126ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.904m | 8.001ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| rom_ctrl_kmac_err_chk | 1.175m | 24.354ms | 48 | 50 | 96.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.134m | 983.989ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 2.934m | 67.780ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.253m | 17.277ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 92 | 95 | 96.84 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.443h | 35.102ms | 5 | 50 | 10.00 |
| V3 | TOTAL | 5 | 50 | 10.00 | |||
| TOTAL | 448 | 500 | 89.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.59 | 96.97 | 93.30 | 97.88 | 100.00 | 98.69 | 97.89 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
3.rom_ctrl_stress_all_with_rand_reset.48364039303513242072718850416755839170290601944282318848367852754193823205985
Line 308, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15733909363 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15733909363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rom_ctrl_stress_all_with_rand_reset.54182365945588144027701440818360916110589752031154887849667874351204774604555
Line 378, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 48431158212 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 48431158212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 9 failures:
2.rom_ctrl_stress_all_with_rand_reset.5394687408901598749143223419862083691195549054924608526254348697570685214208
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11337317828 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x687cefd7
UVM_INFO @ 11337317828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rom_ctrl_stress_all_with_rand_reset.96565375369765268247022970003370537467025297222073652363202582890304418219490
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11253878561 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xde8f49e0
UVM_INFO @ 11253878561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
0.rom_ctrl_stress_all_with_rand_reset.17675553093133234961058456894336356016764753597176025075727423339238165636037
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8c32a5f2-3d38-42ab-818a-6dee67335d4f
1.rom_ctrl_stress_all_with_rand_reset.2481787601011390207343737808566273529972724476423268236419036258745920600466
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:217aa4ac-c33a-4d39-abf2-a499496a0145
... and 3 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
Test rom_ctrl_kmac_err_chk has 2 failures.
10.rom_ctrl_kmac_err_chk.42932742825718665387515551133863065377760297857852147710351544476982770108986
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 6591732028 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 6591732028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.rom_ctrl_kmac_err_chk.76451709311414868840230769684626342541487961094937604754659000824412905855182
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 6596776409 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 6596776409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
20.rom_ctrl_corrupt_sig_fatal_chk.39930054526045595157571659248121585354631880421262572670097495266433700074078
Line 274, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 24788315935 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 24788315935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
1.rom_ctrl_passthru_mem_tl_intg_err.14943482206298745175124365178017245798094717385886729614093830830411486937753
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
10.rom_ctrl_corrupt_sig_fatal_chk.68867159678460293234869380024874305895861570156833243637313843569817242166934
Line 305, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
15.rom_ctrl_stress_all.73693405254189495658709769667532937512271226645642493479357796428430968759625
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 80210513767 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x632e9adf
UVM_INFO @ 80210513767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rom_ctrl_stress_all.37148925084110529381165630692754101073798660528366615748712127053349132393920
Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40087976457 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xca0fe6ff
UVM_INFO @ 40087976457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---