ROM_CTRL/64KB Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.339m	8.525ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.160s	7.353ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	30.430s	7.822ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.500s	68.768ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.810s	19.544ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.740s	24.184ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	30.430s	7.822ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	19.544ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	26.720s	3.466ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.600s	15.730ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.140s	17.507ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.956m	141.778ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.176m	58.556ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.150s	17.781ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.180s	17.039ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.180s	17.039ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.160s	7.353ms	5	5	100.00
		rom_ctrl_csr_rw	30.430s	7.822ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	19.544ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.170s	28.013ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.160s	7.353ms	5	5	100.00
		rom_ctrl_csr_rw	30.430s	7.822ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	19.544ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.170s	28.013ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.333m	24.885ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.119m	11.705ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.844m	14.703ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.119m	11.705ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.119m	11.705ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.119m	11.705ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.339m	8.525ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.339m	8.525ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.339m	8.525ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.844m	14.703ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.176m	58.556ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	22.909m	945.089ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.333m	24.885ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.119m	11.705ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.983h	90.956ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.88	91.85	97.72	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.2155992480533778214455462358019131528924121164642101672611771798379079484910
    Line 304, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9644307823 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9644307823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.89247257824025668976159347079308006008125069040388685938253809355637228012762
    Line 376, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33060731589 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33060731589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.45783240134282418130152631105722852723835828860821274950963325357942941685184
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10596888088 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1ef5f560
  UVM_INFO @ 10596888088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.17664021535771958037593842066978953400001674473134483851325958441197447280282
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10023216205 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc43fb2c5
  UVM_INFO @ 10023216205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.22515145371511544656532834466771304833732315502934484086532545057847347263868
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1cc32abd-05f4-448b-a988-98c7fb246512
```
  - 6.rom_ctrl_stress_all_with_rand_reset.68125995312250748805709040204916627034228877970964358792809496779291251622811
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3886e23c-69d4-4190-8ac9-aaae0cf03edd
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 20.rom_ctrl_stress_all.42347335510334671098834899036997349462058961268802222656511551624085328047185
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40028772514 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x821937c2
  UVM_INFO @ 40028772514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_smoke has 1 failures.
  - 46.rom_ctrl_smoke.78782378091164377358889248937189658145783643164568978617272513716672564525065
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40014904846 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x11f131bb
  UVM_INFO @ 40014904846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `32d52b8d41`