8cb25a6867| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.386m | 17.072ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 39.410s | 10.230ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 32.050s | 4.295ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 23.590s | 3.036ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 28.410s | 3.474ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 32.170s | 35.530ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 32.050s | 4.295ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 28.410s | 3.474ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 25.920s | 3.272ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 31.230s | 16.278ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 36.040s | 16.719ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 5.669m | 33.459ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.222m | 117.112ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 34.210s | 4.305ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 37.460s | 4.222ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 37.460s | 4.222ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 39.410s | 10.230ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.050s | 4.295ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 28.410s | 3.474ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 36.760s | 15.274ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 39.410s | 10.230ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.050s | 4.295ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 28.410s | 3.474ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 36.760s | 15.274ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 238 | 240 | 99.17 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.270m | 112.379ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.808m | 7.070ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.850m | 3.905ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.808m | 7.070ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.808m | 7.070ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.808m | 7.070ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.386m | 17.072ms | 47 | 50 | 94.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.386m | 17.072ms | 47 | 50 | 94.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.386m | 17.072ms | 47 | 50 | 94.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.850m | 3.905ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 1.222m | 117.112ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.974m | 540.975ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.270m | 112.379ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.808m | 7.070ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.570h | 60.514ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 453 | 500 | 90.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.59 | 96.97 | 93.16 | 97.88 | 100.00 | 98.69 | 98.04 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
0.rom_ctrl_stress_all_with_rand_reset.53780605459085084840552907651202500199681381623455392821794060108499791736834
Line 279, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6320503376 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6320503376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.30229363463590636188621002312251809453395712745609777049491464523934876561841
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8252451224 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8252451224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
11.rom_ctrl_stress_all_with_rand_reset.25936250707318620494021642003194624083622360916044211897072664663810447914026
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10005072509 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5fb8047e
UVM_INFO @ 10005072509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.rom_ctrl_stress_all_with_rand_reset.6468766581304333137092880096827034406421441825158951856091093330734021175855
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10006369433 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf69623e7
UVM_INFO @ 10006369433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
4.rom_ctrl_stress_all_with_rand_reset.114518543638373007704226654148527616573660595713657011760185684104099977643320
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:801d3891-a310-466f-8eee-fecad1f4a49e
5.rom_ctrl_stress_all_with_rand_reset.24464883006664331668015583837810181223553886989317681776551419980301116010966
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:47dc9021-6657-441b-8316-d8be15dc2b11
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 4 failures:
Test rom_ctrl_stress_all has 1 failures.
5.rom_ctrl_stress_all.47330053425398603026072794368870432279014046144867371567857393381667263242278
Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40156904476 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x347dedc3
UVM_INFO @ 40156904476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_smoke has 3 failures.
6.rom_ctrl_smoke.53267158996985966797634725224735314579652702232969511648283759346362716115495
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40021627095 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x81532d01
UVM_INFO @ 40021627095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rom_ctrl_smoke.11794966090473097598358600078741290526163844577844078372942835448834538194334
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40009949961 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x46a4571c
UVM_INFO @ 40009949961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
36.rom_ctrl_stress_all_with_rand_reset.84274680748770458131689538094543418570964168310257922793832442679359284101397
Line 708, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 983772323668 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 983772323668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_kmac_err_chk has 1 failures.
38.rom_ctrl_kmac_err_chk.110237006874781057015163710352981677299375815390452852920129167313501500454678
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 5499087299 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 5499087299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
11.rom_ctrl_passthru_mem_tl_intg_err.4194921979065794843224586228084324699466083529690590050352492261200890880076
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---