ROM_CTRL/64KB Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.372m	8.047ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	40.700s	40.821ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.890s	57.110ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	28.480s	3.433ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.780s	10.268ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.190s	4.389ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.890s	57.110ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.780s	10.268ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	26.840s	3.294ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.850s	4.340ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.820s	16.213ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.283m	22.984ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.151m	31.988ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.430s	4.260ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	38.070s	4.180ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	38.070s	4.180ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	40.700s	40.821ms	5	5	100.00
		rom_ctrl_csr_rw	32.890s	57.110ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.780s	10.268ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.060s	16.695ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	40.700s	40.821ms	5	5	100.00
		rom_ctrl_csr_rw	32.890s	57.110ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.780s	10.268ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.060s	16.695ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.203m	102.950ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.119m	5.485ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.880m	3.733ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.119m	5.485ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.119m	5.485ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.119m	5.485ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.372m	8.047ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.372m	8.047ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.372m	8.047ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.880m	3.733ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.151m	31.988ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.845m	95.433ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.203m	102.950ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.119m	5.485ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.715h	62.457ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.50	96.97	93.02	97.88	100.00	98.37	97.89	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.10729565384219259111763686246668205796573676757086087137879183250300347968271
    Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10718591629 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10718591629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.56137913099650495356201917425552045084591524471795493525755315530519282451342
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4156733832 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4156733832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.102751873597367590803216793087091822311170625186799528333912019413972401287728
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10245743519 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc0f65103
  UVM_INFO @ 10245743519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.79679871635243407125154514263769280688153990299529793322036115952790563690315
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013064385 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x81fcf5f9
  UVM_INFO @ 10013064385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.67982181990100145095370972991677822714335842414570978339031419145588401510609
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7c20b17e-a0b3-48d3-9b87-ab31471543ab
```
  - 35.rom_ctrl_stress_all_with_rand_reset.56534246408037089035261824244345878703834239138675642459623650781472247548699
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:144b7f42-cc83-462e-86c7-6cea3df5064e
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 2.rom_ctrl_smoke.5230310206238759990493784456009479990425489031784454639033548034386110071977
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40009715552 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x46bad4c9
  UVM_INFO @ 40009715552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 35.rom_ctrl_stress_all.54153275237018074220503028315105063260990721407225980786092422721419618484493
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40116189464 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xc9f08a90
  UVM_INFO @ 40116189464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.rom_ctrl_stress_all_with_rand_reset.49678429901359821849786090270781013730401823763363727241110063476312259620244
    Line 643, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 686836464733 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 686836464733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a182fcef27`