01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.302m | 22.477ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 36.200s | 3.582ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 33.100s | 4.263ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 30.510s | 3.865ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 31.750s | 4.107ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 33.660s | 4.473ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 33.100s | 4.263ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 31.750s | 4.107ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 32.920s | 4.067ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 22.010s | 20.453ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.070s | 4.188ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.704m | 48.185ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.191m | 38.845ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 34.270s | 4.361ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 36.740s | 6.973ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 36.740s | 6.973ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 36.200s | 3.582ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.100s | 4.263ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 31.750s | 4.107ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 33.240s | 8.745ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 36.200s | 3.582ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.100s | 4.263ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 31.750s | 4.107ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 33.240s | 8.745ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.312m | 47.312ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.215m | 3.568ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.952m | 8.852ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.215m | 3.568ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.215m | 3.568ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.215m | 3.568ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.302m | 22.477ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.302m | 22.477ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.302m | 22.477ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.952m | 8.852ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.191m | 38.845ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.527m | 93.325ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.312m | 47.312ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.215m | 3.568ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 93 | 95 | 97.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.354h | 158.938ms | 6 | 50 | 12.00 |
| V3 | TOTAL | 6 | 50 | 12.00 | |||
| TOTAL | 453 | 500 | 90.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.50 | 96.97 | 93.02 | 97.88 | 100.00 | 98.37 | 97.89 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
1.rom_ctrl_stress_all_with_rand_reset.66170386305398338968855792513195235407520529873780766581460410798741838454720
Line 342, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29507719986 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29507719986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_ctrl_stress_all_with_rand_reset.3042763870359982493359614302854052919904691460186922246844030654181213940211
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9813221137 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9813221137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
0.rom_ctrl_stress_all_with_rand_reset.41192511615434972040958789215701355173203722244594146919995646017501741519808
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10007798712 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf73ec34f
UVM_INFO @ 10007798712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rom_ctrl_stress_all_with_rand_reset.5715412976149353363296216129117827864141886989247158173556022785698560386824
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10004205959 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x92aaf6d8
UVM_INFO @ 10004205959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
5.rom_ctrl_stress_all_with_rand_reset.33496650553111117122803869661027625397191255365418900127668002118210392314357
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:fffb8c6c-4f9e-4402-a488-89db2967f672
15.rom_ctrl_stress_all_with_rand_reset.104541194982311948197982819031596427048652332985299021895707150207030359637185
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3df7310f-5115-46ce-95f6-86850c932402
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.rom_ctrl_passthru_mem_tl_intg_err.32318347244795033946763817028862644735396746558981643703084701818586382800983
Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
11.rom_ctrl_smoke.21723355094386389002666708854668864780074927413085593212462607564299074330871
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40014759106 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x53b9c62d
UVM_INFO @ 40014759106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
32.rom_ctrl_corrupt_sig_fatal_chk.44260144465274662353715165677271406540499884415172027503905208020232382489015
Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 41735915815 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 41735915815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---