ROM_CTRL/64KB Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.337m	15.809ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	36.360s	27.948ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.520s	4.445ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.610s	3.970ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.970s	61.021ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.090s	4.237ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.520s	4.445ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.970s	61.021ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	27.220s	12.496ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.480s	17.365ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.010s	4.901ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.827m	29.250ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.145m	32.024ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.270s	4.101ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	31.470s	3.136ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	31.470s	3.136ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	36.360s	27.948ms	5	5	100.00
		rom_ctrl_csr_rw	32.520s	4.445ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.970s	61.021ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	30.400s	15.393ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	36.360s	27.948ms	5	5	100.00
		rom_ctrl_csr_rw	32.520s	4.445ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.970s	61.021ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	30.400s	15.393ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.088m	49.174ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.160m	7.170ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.889m	7.270ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.160m	7.170ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.160m	7.170ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.160m	7.170ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.337m	15.809ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.337m	15.809ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.337m	15.809ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.889m	7.270ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.145m	32.024ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.089m	616.630ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.088m	49.174ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.160m	7.170ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.336h	19.356ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.33	96.89	92.28	97.72	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.98035340294450479302973136313164852599830450646350918640022341537902813582406
    Line 560, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 214922003636 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 214922003636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.1449797910416024879518156284841381790145929891171172144010082998545241918808
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2340051348 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2340051348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.47972505056734467163671550578408014661780979258530784894595846537915175038307
    Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11439340012 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9f96d1c9
  UVM_INFO @ 11439340012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rom_ctrl_stress_all_with_rand_reset.28076569867443215121573922808731663212070516102797670092990013359096039659538
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012935091 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf9ed71fe
  UVM_INFO @ 10012935091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.88660870899371494230548067224256163098041518694755847308092637868962285898015
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:66b84771-0870-4a25-a9c6-dc7cab63e58f
```
  - 5.rom_ctrl_stress_all_with_rand_reset.21337300224331317656233804056502992603552636102757957862831268607979050304091
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cf729047-4ae6-47ef-b2e1-eea136ddb5cb
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 14.rom_ctrl_smoke.98301993290305316257043663873507422858508372077454117167364714821165976206947
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40015398606 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x84f0e8ff
  UVM_INFO @ 40015398606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 29.rom_ctrl_stress_all.44760031951981052666189043072546224672740716271724332843519604035905039938665
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40263729364 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe65988bf
  UVM_INFO @ 40263729364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.88422174122383905787765711661908083058259359746932193913912094960738403158446
    Line 908, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 749963770084 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 749963770084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a8c9c17a8c`