ROM_CTRL/64KB Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.516m	8.661ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	30.850s	3.327ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.650s	12.566ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.190s	16.039ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	29.260s	14.300ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.060s	18.206ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.650s	12.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.260s	14.300ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.150s	8.067ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	33.770s	8.496ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.550s	4.171ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.283m	102.979ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.215m	35.530ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	35.040s	66.963ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.020s	18.639ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.020s	18.639ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	30.850s	3.327ms	5	5	100.00
		rom_ctrl_csr_rw	33.650s	12.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.260s	14.300ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.690s	17.352ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	30.850s	3.327ms	5	5	100.00
		rom_ctrl_csr_rw	33.650s	12.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.260s	14.300ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.690s	17.352ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.255m	23.599ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.159m	17.668ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.920m	7.796ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.159m	17.668ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.159m	17.668ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.159m	17.668ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.516m	8.661ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.516m	8.661ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.516m	8.661ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.920m	7.796ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.215m	35.530ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.798m	518.029ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.255m	23.599ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.159m	17.668ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.589h	36.132ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.89	91.99	97.72	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.69616585344085685618075676950792327943280376785450209157493251978833703548243
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106321487 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106321487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.72843270965214840580759086101685931280424410973000389251519847852254642779892
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1358599136 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1358599136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.106863048618283088410241338132549580419154628664047122575820935975987745063162
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:50b69a13-6300-4b44-98d5-734a70ec0258
```
  - 26.rom_ctrl_stress_all_with_rand_reset.102585059052687871568688923063561802334137931618675402173447342914421479806762
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:96b7b936-94d9-4bc9-94fc-ceff9a4b4663
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 3.rom_ctrl_stress_all.47943379530878091697565191759677699088934288231795403960177575757453331799559
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40316220938 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x682e90ef
  UVM_INFO @ 40316220938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_smoke has 1 failures.
  - 35.rom_ctrl_smoke.77883222729999176854003379927865822235115036472139718016714805905494052779959
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40015315244 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x47f42430
  UVM_INFO @ 40015315244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.50293241855526894542102428319709907358001322261196933335955739088618162383461
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12094117360 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x4fe5a612
  UVM_INFO @ 12094117360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.45075411047666376063126460379845625877477165746462756361382085201250627244879
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10011581205 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x30d44778
  UVM_INFO @ 10011581205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.rom_ctrl_stress_all_with_rand_reset.97927699854192276347267169370159836097317562604114738842862427259044001373685
    Line 409, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 215943719636 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 215943719636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `dd5ad5fb77`