ROM_CTRL/64KB Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.324m	33.475ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.670s	8.794ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	29.090s	14.825ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	33.210s	9.301ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	22.880s	5.896ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.380s	8.057ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	29.090s	14.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	22.880s	5.896ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	22.150s	2.230ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.060s	8.325ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.620s	9.121ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.127m	104.713ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.186m	28.329ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.040s	17.040ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.930s	4.675ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.930s	4.675ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.670s	8.794ms	5	5	100.00
		rom_ctrl_csr_rw	29.090s	14.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	22.880s	5.896ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.920s	4.395ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.670s	8.794ms	5	5	100.00
		rom_ctrl_csr_rw	29.090s	14.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	22.880s	5.896ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.920s	4.395ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.722m	36.227ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.984m	15.205ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.000m	16.597ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.984m	15.205ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.984m	15.205ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.984m	15.205ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.324m	33.475ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.324m	33.475ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.324m	33.475ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.000m	16.597ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.186m	28.329ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.633m	168.714ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.722m	36.227ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.984m	15.205ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.087h	80.341ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.72	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.52881253722488437695082414548563605953049088880731234992269670275391614726733
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 383420501 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 383420501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.110458756142868188370211575910630416531521700340171739640752768139816930839397
    Line 387, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25809221951 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25809221951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.76928167064967408236195302809263261092735813543475701008281904968033954633365
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10014362438 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2a70ba1c
  UVM_INFO @ 10014362438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.12762863693603368975614648050495500708139269439278621686906579669016943272834
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10020771858 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x425e74e7
  UVM_INFO @ 10020771858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.32891660442758812024233875840616515529281730500634330351755076115971150410138
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:13406445-0342-4962-b7cf-fc40fd53c9f6
```
  - 19.rom_ctrl_stress_all_with_rand_reset.16932212585302982371753504449835025403036074348099092114061381364770834670396
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4283a1a0-6ade-4ca5-8523-294f707531df
```
  - ... and 3 more failures.

ROM_CTRL/64KB Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `548a3880d8`