8fdb25c8d9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.368m | 75.164ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 37.240s | 7.550ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 32.210s | 5.708ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 21.340s | 8.919ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 26.110s | 62.086ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 30.350s | 8.046ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 32.210s | 5.708ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 26.110s | 62.086ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 25.310s | 5.869ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 22.800s | 6.029ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 32.720s | 4.962ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 4.138m | 25.312ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.131m | 104.464ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 34.290s | 8.601ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 37.470s | 16.897ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 37.470s | 16.897ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 37.240s | 7.550ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.210s | 5.708ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 26.110s | 62.086ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 34.240s | 39.459ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 37.240s | 7.550ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.210s | 5.708ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 26.110s | 62.086ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 34.240s | 39.459ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.222m | 102.700ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.735m | 1.899ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.900m | 16.092ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.735m | 1.899ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.735m | 1.899ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.735m | 1.899ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.368m | 75.164ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.368m | 75.164ms | 48 | 50 | 96.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.368m | 75.164ms | 48 | 50 | 96.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.900m | 16.092ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.131m | 104.464ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 14.430m | 78.218ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.222m | 102.700ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.735m | 1.899ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.258h | 134.742ms | 7 | 50 | 14.00 |
| V3 | TOTAL | 7 | 50 | 14.00 | |||
| TOTAL | 453 | 500 | 90.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.26 | 96.89 | 91.99 | 97.68 | 100.00 | 98.62 | 97.30 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
1.rom_ctrl_stress_all_with_rand_reset.74371285506114170365853656549812692790491958972223063108090131050986543033099
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7156279216 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7156279216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rom_ctrl_stress_all_with_rand_reset.93311281022373100538146317217968107280418117872185341182197980484517920709735
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 429897524 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 429897524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 12 failures:
0.rom_ctrl_stress_all_with_rand_reset.98415314182689395066914662600170696608060768743831116357203694877076674176591
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10005137985 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7408b021
UVM_INFO @ 10005137985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rom_ctrl_stress_all_with_rand_reset.528556683163780674431346365414720605245442389014287619749210600336847368687
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10311380282 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x792808db
UVM_INFO @ 10311380282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
25.rom_ctrl_stress_all_with_rand_reset.93077909088337478784401856192748316261954811541677840030421969721557694910684
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9aa93af9-35ca-43e3-9bde-c1ed5673828a
28.rom_ctrl_stress_all_with_rand_reset.114586644929968037134353462983891853653035053284031828714831479345726461583734
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:476680ab-3c92-40bc-9bf9-228104b45f9d
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
38.rom_ctrl_smoke.53608209202878702246490639378856872613441836546600713778935334428988283293362
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40031270784 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x5127b325
UVM_INFO @ 40031270784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rom_ctrl_smoke.13326391538806675531070812183213587229766382901852663448741208038279787243064
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40013460243 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xd3e78a7b
UVM_INFO @ 40013460243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
8.rom_ctrl_corrupt_sig_fatal_chk.46928169042588544349204047274182830322472506949614712775189025785236064920454
Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
12.rom_ctrl_stress_all.38622551650440430954260783938416382624941700187131030670844332974408171600395
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest/run.log
UVM_ERROR @ 14168626646 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 14168626646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---