ROM_CTRL/64KB Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.436m	31.039ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	24.150s	2.839ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.910s	8.703ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	25.160s	5.965ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	33.310s	4.238ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.280s	4.113ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.910s	8.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.310s	4.238ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	32.640s	24.517ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.870s	57.332ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.550s	3.968ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.655m	50.243ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.177m	17.497ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.130s	17.805ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	33.750s	12.881ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	33.750s	12.881ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	24.150s	2.839ms	5	5	100.00
		rom_ctrl_csr_rw	32.910s	8.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.310s	4.238ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	36.390s	8.635ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	24.150s	2.839ms	5	5	100.00
		rom_ctrl_csr_rw	32.910s	8.703ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.310s	4.238ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	36.390s	8.635ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.673m	80.469ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.112m	15.379ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.855m	7.762ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.112m	15.379ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.112m	15.379ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.112m	15.379ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.436m	31.039ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.436m	31.039ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.436m	31.039ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.855m	7.762ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.177m	17.497ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.777m	119.987ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.673m	80.469ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.112m	15.379ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.974h	50.567ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.68	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 33 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.18812872682321626774202022229442229246459606285944293191218880539244537016820
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108352332 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108352332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.10198073040921002186554637602785045979723521891203175039118052455638529925425
    Line 269, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14756176412 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14756176412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.108401406720279267003042233581899682891190982899680178455403044940442707723178
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10587910995 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x13ed0835
  UVM_INFO @ 10587910995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_stress_all_with_rand_reset.92137700226563147257822499634947001983210609961585863444445870380335096867048
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003485487 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5dc13bf3
  UVM_INFO @ 10003485487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 7.rom_ctrl_stress_all.37766488478668398402329925389040092426495235881447235004381004448780168568936
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40182073305 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6d141d
  UVM_INFO @ 40182073305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_smoke has 1 failures.
  - 44.rom_ctrl_smoke.89288543677222352580063744655931147606688705257080986380441911917314932814336
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40009864833 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x75b1622e
  UVM_INFO @ 40009864833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 9.rom_ctrl_passthru_mem_tl_intg_err.100104145131346700888716520901688997326951818557820377556075469897877190217539
    Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.rom_ctrl_stress_all_with_rand_reset.57235342481444009820754168119369612350920738725789513420620750440422515272798
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:976303d4-d2b3-4b1b-9a68-476f1805d571
```

ROM_CTRL/64KB Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25e609d6bb`