3fd3528c8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.327m | 14.325ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 39.370s | 4.236ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 34.090s | 4.435ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 32.190s | 4.145ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 32.350s | 4.752ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 31.970s | 14.828ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 34.090s | 4.435ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 32.350s | 4.752ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 32.390s | 7.725ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 33.350s | 4.351ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 34.550s | 49.837ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.936m | 29.036ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.178m | 94.623ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.500s | 4.235ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 35.760s | 7.846ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 35.760s | 7.846ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 39.370s | 4.236ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 34.090s | 4.435ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.350s | 4.752ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.720s | 40.175ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 39.370s | 4.236ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 34.090s | 4.435ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.350s | 4.752ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.720s | 40.175ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 238 | 240 | 99.17 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.445m | 150.707ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.186m | 17.482ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.936m | 8.294ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.186m | 17.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.186m | 17.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.186m | 17.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.327m | 14.325ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.327m | 14.325ms | 48 | 50 | 96.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.327m | 14.325ms | 48 | 50 | 96.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.936m | 8.294ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.178m | 94.623ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.020m | 201.736ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.445m | 150.707ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.186m | 17.482ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.962h | 55.712ms | 16 | 50 | 32.00 |
| V3 | TOTAL | 16 | 50 | 32.00 | |||
| TOTAL | 461 | 500 | 92.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.28 | 96.89 | 92.13 | 97.68 | 100.00 | 98.62 | 97.30 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
0.rom_ctrl_stress_all_with_rand_reset.15138329768004914523044575310733787141178966796888320520299466480786520752114
Line 388, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67839304899 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 67839304899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_ctrl_stress_all_with_rand_reset.59489495725117586292456115685260626956922953140572678458134491680061470388259
Line 379, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 53561814321 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 53561814321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
11.rom_ctrl_stress_all_with_rand_reset.110772567164222951106062204938209802590155879682932404943961983271253828867644
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10606802068 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x34ab00dc
UVM_INFO @ 10606802068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rom_ctrl_stress_all_with_rand_reset.73465651025483364262354568592684177431076593917741596627299703137585488882814
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003692152 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe2507ff8
UVM_INFO @ 10003692152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
Test rom_ctrl_smoke has 2 failures.
4.rom_ctrl_smoke.56483549517228731765791909428013867553686605948957956943648157931657612112460
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40010994484 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xba3c0ba
UVM_INFO @ 40010994484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rom_ctrl_smoke.46061911079785380615933690771329590110201144048817247502485542673357068171047
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40017442107 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x38b99df6
UVM_INFO @ 40017442107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all has 1 failures.
44.rom_ctrl_stress_all.110889928112858728070153034970082297042758243742969728639313342491679446714970
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40361859196 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa06d0c2f
UVM_INFO @ 40361859196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
17.rom_ctrl_stress_all_with_rand_reset.56638240521484800773116554179072292914155527750326824936493082147735088730770
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e79b520d-6443-40ff-8993-f673ede3cd4c
45.rom_ctrl_stress_all_with_rand_reset.27663574402235715063539291673710033941044085371579988141226816889673489761615
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:94d7e301-9439-4d98-8eed-383fda34f09f
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
15.rom_ctrl_kmac_err_chk.18864366198433861944409353993842388921431334188202124606483976592742352559438
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 6594259381 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 6594259381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
36.rom_ctrl_corrupt_sig_fatal_chk.47695667985120100577844646139665582612950589037152759666151739214436781615980
Line 304, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---