ROM_CTRL/64KB Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.388m	34.976ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	35.770s	3.775ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.810s	18.363ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.140s	17.110ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.230s	3.914ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.410s	22.107ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.810s	18.363ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.230s	3.914ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	32.200s	4.187ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.000s	4.376ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.640s	4.334ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.582m	25.230ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.185m	17.127ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	32.160s	3.857ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.470s	25.217ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.470s	25.217ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	35.770s	3.775ms	5	5	100.00
		rom_ctrl_csr_rw	32.810s	18.363ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.230s	3.914ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.260s	4.795ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	35.770s	3.775ms	5	5	100.00
		rom_ctrl_csr_rw	32.810s	18.363ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.230s	3.914ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.260s	4.795ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.183m	100.614ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.813m	815.389us	5	5	100.00
		rom_ctrl_tl_intg_err	2.900m	7.763ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.813m	815.389us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.813m	815.389us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.813m	815.389us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.388m	34.976ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.388m	34.976ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.388m	34.976ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.900m	7.763ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
		rom_ctrl_kmac_err_chk	1.185m	17.127ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.970m	118.451ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.183m	100.614ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.813m	815.389us	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.931h	99.266ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			454	500	90.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 31 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.12766934903319619658569418199726595519750445601666695490700761039348761061704
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 908633217 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 908633217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.35503457880266856559690846768204747000559793755487598538336811522190721671821
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4653936116 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4653936116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.22672597036543826045720376660024058703100316561833327590634611128321298805790
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10017768876 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf362761e
  UVM_INFO @ 10017768876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.89570690759870909056198939253881429436800729362342389776704515212390811052738
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004443814 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2c9cf25c
  UVM_INFO @ 10004443814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.108692239454334254777161199400016475858331342953372858315741020878533856998914
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1fbce146-b39b-4709-b50d-9e50145315f4
```
  - 15.rom_ctrl_stress_all_with_rand_reset.15771245812792291153860745304521603536617692970510303579932039236016915153827
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a273d4a4-cacf-418b-965e-f7725b1d5864
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 1.rom_ctrl_corrupt_sig_fatal_chk.32852731791861838170929428876082766437358308834992356135240762573146600429997
    Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_corrupt_sig_fatal_chk.42427396136889319894170335576053645014690033331702298408722253296846279604307
    Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all has 2 failures.
  - 7.rom_ctrl_stress_all.104420351827680063775249561497849351611060901202519039023987610808470042358565
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40009718405 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x447c5b42
  UVM_INFO @ 40009718405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.rom_ctrl_stress_all.32873948746437804376336702366115244926387086421828164195416992111792393614228
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40028850000 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x71b4c868
  UVM_INFO @ 40028850000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 19.rom_ctrl_kmac_err_chk.112786624632082059451946513873472878937078075179410024689395111490674125181172
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 5489041791 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5489041791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be1c4a4f52`