ROM_CTRL/64KB Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.256m	8.367ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.090s	57.491ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.690s	9.984ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.940s	3.933ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	20.330s	10.935ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.260s	4.268ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.690s	9.984ms	20	20	100.00
		rom_ctrl_csr_aliasing	20.330s	10.935ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	33.260s	29.304ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.750s	20.516ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.160s	28.529ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.457m	108.043ms	47	50	94.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.183m	35.516ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	32.370s	12.722ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.650s	17.307ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.650s	17.307ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.090s	57.491ms	5	5	100.00
		rom_ctrl_csr_rw	32.690s	9.984ms	20	20	100.00
		rom_ctrl_csr_aliasing	20.330s	10.935ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.030s	4.105ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.090s	57.491ms	5	5	100.00
		rom_ctrl_csr_rw	32.690s	9.984ms	20	20	100.00
		rom_ctrl_csr_aliasing	20.330s	10.935ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.030s	4.105ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.705m	19.067ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.082m	3.801ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.978m	4.979ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.082m	3.801ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.082m	3.801ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.082m	3.801ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.256m	8.367ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.256m	8.367ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.256m	8.367ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.978m	4.979ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.183m	35.516ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.928m	114.550ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.705m	19.067ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.082m	3.801ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.902h	99.046ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	96.89	91.99	97.68	100.00	98.28	97.30	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.81229234114803041541292358788009485178068766396081067477346300298502883596499
    Line 538, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18310285662 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18310285662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.41875060481305444797936582861634826300251894043044991948321911991364167311326
    Line 378, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15426912446 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15426912446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.30633616627225854447950448609790749146515937357669600931819193494659686812651
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006581583 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd150295d
  UVM_INFO @ 10006581583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.67140198440292204752042815689029559982901026536960641262832034569492285671664
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10019006114 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa73583ae
  UVM_INFO @ 10019006114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all has 3 failures.
  - 0.rom_ctrl_stress_all.104391433683906345814043467647938327854316902096536465392133047124552564839096
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40010379315 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x121c0767
  UVM_INFO @ 40010379315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_stress_all.10124063626369602298679118051149287176778640780757591554822875929939811288990
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40278757366 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xd164ad7
  UVM_INFO @ 40278757366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test rom_ctrl_smoke has 1 failures.
  - 40.rom_ctrl_smoke.64503717565188784750420500434650304481373768199949838577192787251397998811004
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40012874890 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbf297264
  UVM_INFO @ 40012874890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.86308182539948315661608649367227513618701135293628920029088436154744359926784
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b091684e-3613-4022-a7a8-333740e0b068
```
  - 3.rom_ctrl_stress_all_with_rand_reset.110654372130549290014247690343994547614573481390444526961850976219174609740753
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:43fd60c8-683a-4841-b09b-75758a396c50
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 11.rom_ctrl_kmac_err_chk.9904418390084165734138346366770845064117252453732342520809034294007555268203
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 5493219503 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5493219503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8db2a18db1`