3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.256m | 28.779ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 35.260s | 25.886ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 30.540s | 4.172ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 23.650s | 42.675ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 29.710s | 15.461ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 32.830s | 4.169ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 30.540s | 4.172ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 29.710s | 15.461ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 27.770s | 3.544ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 31.640s | 4.275ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.310s | 14.728ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.243m | 98.691ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.165m | 32.158ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.520s | 8.234ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 37.700s | 18.355ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 37.700s | 18.355ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 35.260s | 25.886ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 30.540s | 4.172ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 29.710s | 15.461ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.900s | 4.293ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 35.260s | 25.886ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 30.540s | 4.172ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 29.710s | 15.461ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.900s | 4.293ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.136m | 90.621ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.151m | 4.486ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.934m | 4.136ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.151m | 4.486ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.151m | 4.486ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.151m | 4.486ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.256m | 28.779ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.256m | 28.779ms | 48 | 50 | 96.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.256m | 28.779ms | 48 | 50 | 96.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.934m | 4.136ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.165m | 32.158ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.930m | 197.098ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.136m | 90.621ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.151m | 4.486ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 1.363h | 19.989ms | 5 | 50 | 10.00 |
| V3 | TOTAL | 5 | 50 | 10.00 | |||
| TOTAL | 452 | 500 | 90.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.16 | 96.89 | 91.85 | 97.68 | 100.00 | 98.28 | 97.30 | 98.14 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
0.rom_ctrl_stress_all_with_rand_reset.94986197557875940418272633266749315007018588633574488473373945503199750079767
Line 337, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10687739735 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10687739735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.82800697951785583778445815987472056321866164546289997090285138124275449055735
Line 384, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19838858804 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19838858804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
3.rom_ctrl_stress_all_with_rand_reset.7009662015187717878770270496126502802036840971642321549340110797695453133028
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10012648768 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe69a4693
UVM_INFO @ 10012648768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rom_ctrl_stress_all_with_rand_reset.98086841136312979857317148152258028607832205664993103147073234424275761317966
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10015186302 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x4d372959
UVM_INFO @ 10015186302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
6.rom_ctrl_stress_all_with_rand_reset.27168098983197848688328717439249971755446662477183215528212545009323078508345
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:46a45a55-9537-410b-8b61-d7b0cf44b868
7.rom_ctrl_stress_all_with_rand_reset.72963251513107921343960013252779876387854057225332638662918879509729874069426
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3f2901f1-3751-4ec7-b0d7-6f761c0ec27e
... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
28.rom_ctrl_smoke.77834027857043120749256874962418159347765153235476201767381259071577287786473
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40015595807 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1bfd68ef
UVM_INFO @ 40015595807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rom_ctrl_smoke.104394230197027681113968377539958781409941494541231194119257257404595816648630
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40008923568 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x13e3e1ec
UVM_INFO @ 40008923568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
43.rom_ctrl_corrupt_sig_fatal_chk.113530943321955981177242129115837244546877565300468770590560099349638212243522
Line 283, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---