b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.404m | 34.285ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 40.560s | 9.156ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 31.080s | 15.439ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 32.850s | 17.026ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 32.930s | 22.177ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 33.490s | 16.016ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 31.080s | 15.439ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 32.930s | 22.177ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 28.850s | 3.936ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 17.310s | 1.539ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 34.050s | 4.209ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.217m | 32.887ms | 46 | 50 | 92.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.209m | 170.409ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.140s | 4.135ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 36.790s | 17.670ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 36.790s | 17.670ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 40.560s | 9.156ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.080s | 15.439ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.930s | 22.177ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 37.860s | 9.237ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 40.560s | 9.156ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.080s | 15.439ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.930s | 22.177ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 37.860s | 9.237ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 236 | 240 | 98.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.421m | 52.199ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.950m | 2.608ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.872m | 3.794ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.950m | 2.608ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.950m | 2.608ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.950m | 2.608ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.404m | 34.285ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.404m | 34.285ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.404m | 34.285ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.872m | 3.794ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.209m | 170.409ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 18.114m | 221.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.421m | 52.199ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.950m | 2.608ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.367h | 31.029ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 457 | 500 | 91.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.21 | 96.89 | 91.99 | 97.68 | 100.00 | 98.28 | 97.30 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
3.rom_ctrl_stress_all_with_rand_reset.50174630693465393129440327886974505071191881839725395931439196145146558497895
Line 324, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10090189284 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10090189284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rom_ctrl_stress_all_with_rand_reset.48187694715817787629531799346018270153598195728133970717726699563915211027437
Line 323, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27172311816 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27172311816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
8.rom_ctrl_stress_all_with_rand_reset.1174084178198072625213896168254296851055188722732699414042442786061372417147
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10008756229 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2e76b344
UVM_INFO @ 10008756229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rom_ctrl_stress_all_with_rand_reset.77776461671813123089378256008007566787457172887771812528262249656583408429726
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10422049691 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbe2252a5
UVM_INFO @ 10422049691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 4 failures:
13.rom_ctrl_stress_all.82293906108535122448773659244109830035549749898764928964829312651392687093735
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40154953680 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x9a48f1a6
UVM_INFO @ 40154953680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rom_ctrl_stress_all.35981378419548232270256527615784874829179792512719227566727075010647259337775
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40189615414 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x19846940
UVM_INFO @ 40189615414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
31.rom_ctrl_stress_all_with_rand_reset.98755075026333142352419287047954845805696217499155480326111734886665028784315
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:40338a8a-7e1c-412e-b7ec-d34b24400694
47.rom_ctrl_stress_all_with_rand_reset.89607635524115543959756786138271262607430398775650266403301726102123517245698
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:c4b34210-6edf-4c13-8498-2394d71a5c0c
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
4.rom_ctrl_corrupt_sig_fatal_chk.25540907390541972766105728125089844968261186388286498592863595804809797862934
Line 286, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 59056755743 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 59056755743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---