ROM_CTRL/64KB Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.422m	45.061ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	38.030s	8.527ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.380s	4.298ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	20.350s	1.974ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.210s	16.477ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.530s	4.974ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.380s	4.298ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.210s	16.477ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.330s	21.696ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	23.550s	2.705ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.270s	17.087ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.619m	38.280ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.083m	7.861ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.980s	5.700ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.510s	4.224ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.510s	4.224ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	38.030s	8.527ms	5	5	100.00
		rom_ctrl_csr_rw	32.380s	4.298ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.210s	16.477ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.590s	3.776ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	38.030s	8.527ms	5	5	100.00
		rom_ctrl_csr_rw	32.380s	4.298ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.210s	16.477ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.590s	3.776ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.756m	35.445ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.864m	623.847us	5	5	100.00
		rom_ctrl_tl_intg_err	2.913m	7.497ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.864m	623.847us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.864m	623.847us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.864m	623.847us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.422m	45.061ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.422m	45.061ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.422m	45.061ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.913m	7.497ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.083m	7.861ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.488m	222.160ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.756m	35.445ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.864m	623.847us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.844h	50.177ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.41071784374327196818657900563111057641804975807854530051383248808366370898639
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1102893551 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1102893551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rom_ctrl_stress_all_with_rand_reset.70093647546634320221973302939220758604884674398912977966508934307925798706365
    Line 416, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33868321551 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33868321551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.51332103031359526072145947958007046157329012756066083021754500032402694897217
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10002580207 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xccd62136
  UVM_INFO @ 10002580207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.41186122090449009965490697568510829149354647823832747298470362351417526605741
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006924008 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe89e545e
  UVM_INFO @ 10006924008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.101306359564197256250968743992017735553152505829774642941453935232127680236150
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:37cc9509-ea51-4f40-9e5d-0106cd849b1c
```
  - 27.rom_ctrl_stress_all_with_rand_reset.53330022966565529898002416298420993874030073798132249458141722650125206697374
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3c13cf48-bf59-4e65-a5ca-8389b8e01f1b
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 12.rom_ctrl_stress_all.6369727003043489292936641717562617759199547363681667506023835777747288264918
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 10303017698 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 10303017698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.23183755557973130181527162321493096104373703848423724191311267730246717931254
    Line 910, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1459851174662 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1459851174662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 38.rom_ctrl_stress_all.51440217806829020676929174646811514964732061399529731652131408394285569161213
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40019112056 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xeff800af
  UVM_INFO @ 40019112056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_smoke has 1 failures.
  - 42.rom_ctrl_smoke.55244674298045651209174576024940050129943156153404132201662690977136201779152
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40010457601 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x68f8cea3
  UVM_INFO @ 40010457601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb56ef55d0`