ROM_CTRL/64KB Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.570s	1.034ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	26.040s	268.909us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	22.440s	986.903us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.360s	249.932us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.890s	259.696us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.930s	270.568us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	22.440s	986.903us	20	20	100.00
		rom_ctrl_csr_aliasing	14.890s	259.696us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.430s	254.634us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.930s	3.538ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.340s	262.669us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	52.900s	819.159us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.270s	7.864ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	21.310s	1.038ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	26.430s	4.109ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	26.430s	4.109ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	26.040s	268.909us	5	5	100.00
		rom_ctrl_csr_rw	22.440s	986.903us	20	20	100.00
		rom_ctrl_csr_aliasing	14.890s	259.696us	5	5	100.00
		rom_ctrl_same_csr_outstanding	21.910s	836.337us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	26.040s	268.909us	5	5	100.00
		rom_ctrl_csr_rw	22.440s	986.903us	20	20	100.00
		rom_ctrl_csr_aliasing	14.890s	259.696us	5	5	100.00
		rom_ctrl_same_csr_outstanding	21.910s	836.337us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.540m	2.252ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.297m	1.174ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.720m	18.672ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.297m	1.174ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.297m	1.174ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.297m	1.174ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.570s	1.034ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.570s	1.034ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.570s	1.034ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.720m	18.672ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.270s	7.864ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.115m	18.393ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.540m	2.252ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.297m	1.174ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.546m	4.781ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.39	96.77	92.13	97.68	100.00	98.19	97.91	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 39.rom_ctrl_stress_all_with_rand_reset.113403574825348526081526379301598429495403745951808249510907809541187525231691
    Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6538969880 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 6538969880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.rom_ctrl_stress_all_with_rand_reset.19784057579243886860595945712133429360571556470673397738638137658630668299372
    Line 81, in log /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1996732331 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1996732331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `78ad89d1aa`