ROM_CTRL/64KB Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 19.820s 989.863us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 20.060s 669.995us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 20.300s 1.020ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 13.170s 1.905ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 13.670s 376.808us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 16.870s 261.589us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 20.300s 1.020ms 20 20 100.00
rom_ctrl_csr_aliasing 13.670s 376.808us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 19.750s 9.788ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 12.350s 346.183us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 25.900s 1.462ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.487m 3.013ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 35.700s 498.504us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 21.870s 3.946ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 28.260s 4.123ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 28.260s 4.123ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 20.060s 669.995us 5 5 100.00
rom_ctrl_csr_rw 20.300s 1.020ms 20 20 100.00
rom_ctrl_csr_aliasing 13.670s 376.808us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.770s 2.101ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 20.060s 669.995us 5 5 100.00
rom_ctrl_csr_rw 20.300s 1.020ms 20 20 100.00
rom_ctrl_csr_aliasing 13.670s 376.808us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.770s 2.101ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.520m 1.576ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.450m 316.632us 5 5 100.00
rom_ctrl_tl_intg_err 3.595m 3.220ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.450m 316.632us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.450m 316.632us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.450m 316.632us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 19.820s 989.863us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 19.820s 989.863us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 19.820s 989.863us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 3.595m 3.220ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
rom_ctrl_kmac_err_chk 35.700s 498.504us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 7.063m 84.797ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.520m 1.576ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.450m 316.632us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.336m 7.330ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 460 460 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.50 96.77 92.56 97.68 100.00 98.55 97.91 99.06

Past Results