ROM_CTRL/64KB Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	15.150s	264.050us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.950s	1.478ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	19.090s	1.019ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.000s	252.398us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.030s	260.925us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.910s	2.223ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	19.090s	1.019ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	260.925us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.140s	611.955us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.260s	1.029ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	24.520s	1.072ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	51.270s	837.877us	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	45.920s	32.860ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	19.030s	1.029ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.180s	254.185us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.180s	254.185us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.950s	1.478ms	5	5	100.00
		rom_ctrl_csr_rw	19.090s	1.019ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	260.925us	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.710s	1.032ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.950s	1.478ms	5	5	100.00
		rom_ctrl_csr_rw	19.090s	1.019ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	260.925us	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.710s	1.032ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.684m	24.837ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.449m	416.780us	5	5	100.00
		rom_ctrl_tl_intg_err	3.457m	1.494ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.449m	416.780us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.449m	416.780us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.449m	416.780us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	15.150s	264.050us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	15.150s	264.050us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	15.150s	264.050us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.457m	1.494ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
		rom_ctrl_kmac_err_chk	45.920s	32.860ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.599m	7.656ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.684m	24.837ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.449m	416.780us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.003m	4.344ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.46	96.77	92.28	97.68	100.00	98.55	97.91	99.06

Failure Buckets

• UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 4.rom_ctrl_stress_all.30774476270353979272115627015510928557229753963719963406443827421081443870176
      Line 69, in log /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 10391068782 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 10391068782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 42.rom_ctrl_kmac_err_chk.85253426083235977605142600136897017814331001500854385734277288203791786999683
      Line 64, in log /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_ERROR @ 32860169379 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 32860169379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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