ROM_CTRL/64KB Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	18.800s	7.651ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	25.060s	262.514us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.350s	256.114us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.370s	1.015ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.420s	285.527us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.060s	4.136ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.350s	256.114us	20	20	100.00
		rom_ctrl_csr_aliasing	14.420s	285.527us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.060s	3.647ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	22.110s	1.024ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	19.310s	276.060us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	57.780s	2.801ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.980s	513.621us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.900s	577.392us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	22.340s	2.137ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	22.340s	2.137ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	25.060s	262.514us	5	5	100.00
		rom_ctrl_csr_rw	14.350s	256.114us	20	20	100.00
		rom_ctrl_csr_aliasing	14.420s	285.527us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.930s	375.172us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	25.060s	262.514us	5	5	100.00
		rom_ctrl_csr_rw	14.350s	256.114us	20	20	100.00
		rom_ctrl_csr_aliasing	14.420s	285.527us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.930s	375.172us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.380m	1.644ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.873m	423.987us	5	5	100.00
		rom_ctrl_tl_intg_err	2.894m	2.066ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.873m	423.987us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.873m	423.987us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.873m	423.987us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	18.800s	7.651ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	18.800s	7.651ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	18.800s	7.651ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.894m	2.066ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.980s	513.621us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.197m	17.542ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.380m	1.644ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.873m	423.987us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.670m	37.231ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.39	96.89	91.99	97.68	100.00	98.28	98.05	98.83

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.83940116751646829171768749369156263431360646651591782166520276897148788954399
    Line 104, in log /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3922272197 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 3922272197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rom_ctrl_stress_all_with_rand_reset.36148716991303293466055647961503861357471266390035625376556320064967548466830
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12924092113 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 12924092113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25b1acbf68`