ROM_CTRL/64KB Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.970s	914.087us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	21.520s	1.068ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.820s	293.341us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.360s	4.994ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.050s	2.277ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	19.930s	1.096ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.820s	293.341us	20	20	100.00
		rom_ctrl_csr_aliasing	14.050s	2.277ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.570s	208.852us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.380s	1.077ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	24.850s	19.933ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.278m	16.527ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.880s	534.298us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	21.900s	2.037ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.920s	290.489us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.920s	290.489us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	21.520s	1.068ms	5	5	100.00
		rom_ctrl_csr_rw	14.820s	293.341us	20	20	100.00
		rom_ctrl_csr_aliasing	14.050s	2.277ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.290s	4.344ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	21.520s	1.068ms	5	5	100.00
		rom_ctrl_csr_rw	14.820s	293.341us	20	20	100.00
		rom_ctrl_csr_aliasing	14.050s	2.277ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.290s	4.344ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.488m	21.322ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.474m	2.030ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.293m	329.647us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.474m	2.030ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.474m	2.030ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.474m	2.030ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.970s	914.087us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.970s	914.087us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.970s	914.087us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.293m	329.647us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.880s	534.298us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.535m	50.921ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.488m	21.322ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.474m	2.030ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.830m	5.319ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.36	92.13	97.68	100.00	98.55	97.91	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.101730385540696312721541509906014290827204207015828752103325985867790770326997
    Line 144, in log /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4686926232 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 4686926232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_stress_all_with_rand_reset.34390993760478941248398120918093275401129974926613299106025932372567818409268
    Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2612915386 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2612915386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8a1401d614`