SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16599 | 16599 | 0 | 0 |
OutputsKnown_A | 386986544 | 222626475 | 0 | 0 |
gen_no_flops.OutputDelay_A | 386986544 | 222626475 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16599 | 16599 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 386986544 | 222626475 | 0 | 0 |
T1 | 189910 | 156573 | 0 | 0 |
T2 | 1040004 | 763926 | 0 | 0 |
T3 | 87644 | 63761 | 0 | 0 |
T4 | 55837 | 35791 | 0 | 0 |
T5 | 93852 | 20078 | 0 | 0 |
T6 | 53386 | 34471 | 0 | 0 |
T7 | 1175853 | 855826 | 0 | 0 |
T8 | 1396638 | 821399 | 0 | 0 |
T9 | 116232 | 28600 | 0 | 0 |
T10 | 51819 | 31138 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 386986544 | 222626475 | 0 | 0 |
T1 | 189910 | 156573 | 0 | 0 |
T2 | 1040004 | 763926 | 0 | 0 |
T3 | 87644 | 63761 | 0 | 0 |
T4 | 55837 | 35791 | 0 | 0 |
T5 | 93852 | 20078 | 0 | 0 |
T6 | 53386 | 34471 | 0 | 0 |
T7 | 1175853 | 855826 | 0 | 0 |
T8 | 1396638 | 821399 | 0 | 0 |
T9 | 116232 | 28600 | 0 | 0 |
T10 | 51819 | 31138 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 13224784 | 7863211 | 0 | 0 |
gen_no_flops.OutputDelay_A | 13224784 | 7863211 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13224784 | 7863211 | 0 | 0 |
T1 | 5942 | 4989 | 0 | 0 |
T2 | 37060 | 27638 | 0 | 0 |
T3 | 3228 | 2577 | 0 | 0 |
T4 | 1757 | 1103 | 0 | 0 |
T5 | 2908 | 878 | 0 | 0 |
T6 | 1706 | 1063 | 0 | 0 |
T7 | 40365 | 29682 | 0 | 0 |
T8 | 45374 | 28023 | 0 | 0 |
T9 | 3656 | 1112 | 0 | 0 |
T10 | 1611 | 962 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13224784 | 7863211 | 0 | 0 |
T1 | 5942 | 4989 | 0 | 0 |
T2 | 37060 | 27638 | 0 | 0 |
T3 | 3228 | 2577 | 0 | 0 |
T4 | 1757 | 1103 | 0 | 0 |
T5 | 2908 | 878 | 0 | 0 |
T6 | 1706 | 1063 | 0 | 0 |
T7 | 40365 | 29682 | 0 | 0 |
T8 | 45374 | 28023 | 0 | 0 |
T9 | 3656 | 1112 | 0 | 0 |
T10 | 1611 | 962 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11680055 | 6711352 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11680055 | 6711352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11680055 | 6711352 | 0 | 0 |
T1 | 5749 | 4737 | 0 | 0 |
T2 | 31342 | 23009 | 0 | 0 |
T3 | 2638 | 1912 | 0 | 0 |
T4 | 1690 | 1084 | 0 | 0 |
T5 | 2842 | 600 | 0 | 0 |
T6 | 1615 | 1044 | 0 | 0 |
T7 | 35484 | 25817 | 0 | 0 |
T8 | 42227 | 24793 | 0 | 0 |
T9 | 3518 | 859 | 0 | 0 |
T10 | 1569 | 943 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |