Line Coverage for Module :
rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T8,T23 |
1 | 0 | Covered | T1,T12,T24 |
1 | 1 | Covered | T1,T12,T60 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T12,T24 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T60,T61 |
1 | 1 | 1 | Covered | T1,T12,T24 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T61,T62,T81 |
Cond Coverage for Module :
rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Branch Coverage for Module :
rstmgr_leaf_rst
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T12,T60 |
0 |
0 |
1 |
Covered |
T1,T12,T24 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_spi_device
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_spi_device
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T25,T61 |
1 | 0 | Covered | T12,T24,T60 |
1 | 1 | Covered | T12,T60,T61 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T12,T24,T60 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T12,T24,T60 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T12,T24 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_spi_device
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T12,T60,T61 |
0 |
0 |
1 |
Covered |
T12,T24,T60 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T8,T60 |
1 | 0 | Covered | T1,T60,T77 |
1 | 1 | Covered | T1,T60,T77 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T60,T77 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T60,T61 |
1 | 1 | 1 | Covered | T1,T60,T77 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T60,T77 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_spi_host0
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T60,T77 |
0 |
0 |
1 |
Covered |
T1,T60,T77 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T23,T60 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_spi_host1
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_usb
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_usb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T60,T61 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_usb
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_i2c0
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T60,T25 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_i2c0
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_i2c1
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_i2c1
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_i2c2
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T60,T25 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_d0_i2c2
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_daon_por
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_por_io
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_por_usb
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_lc
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc_io
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_lc_io
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_d0_sys
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
Line Coverage for Instance : tb.dut.u_d0_usb_aon
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T23,T60 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T60,T61,T62 |
LINE 72
EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
--------1-------- ---------2-------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T60,T61,T62 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T61,T62 |
1 | 1 | 1 | Covered | T60,T61,T62 |
LINE 104
EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T61,T62,T81 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
68 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 if ((!rst_ni))
-2-: 70 if ((sw_rst_req_q && clr_sw_rst_req))
-3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T60,T61,T62 |
0 |
0 |
1 |
Covered |
T60,T61,T62 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |