Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_d0_spi_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 100.00 96.43 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.47 100.00 100.00 82.35 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 82.35 82.35
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_chk.u_prim_rst_sync 100.00 100.00 100.00 100.00 100.00
gen_rst_chk.u_rst_chk 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_rst_mux 100.00 100.00 100.00 100.00
u_rst_sync 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00

Line Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Line Coverage for Module self-instances :
SCORELINE
96.67 100.00
tb.dut.u_d0_spi_device

SCORELINE
96.67 100.00
tb.dut.u_d0_spi_host0

SCORELINE
96.67 100.00
tb.dut.u_d0_spi_host1

SCORELINE
96.67 100.00
tb.dut.u_d0_usb

SCORELINE
100.00 100.00
tb.dut.u_d0_usb_aon

SCORELINE
96.67 100.00
tb.dut.u_d0_i2c0

SCORELINE
96.67 100.00
tb.dut.u_d0_i2c1

SCORELINE
96.67 100.00
tb.dut.u_d0_i2c2

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.67 90.00
tb.dut.u_d0_spi_device

SCORECOND
96.67 90.00
tb.dut.u_d0_spi_host0

SCORECOND
96.67 90.00
tb.dut.u_d0_spi_host1

SCORECOND
96.67 90.00
tb.dut.u_d0_usb

SCORECOND
100.00 100.00
tb.dut.u_d0_usb_aon

SCORECOND
96.67 90.00
tb.dut.u_d0_i2c0

SCORECOND
96.67 90.00
tb.dut.u_d0_i2c1

SCORECOND
96.67 90.00
tb.dut.u_d0_i2c2

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT1,T8,T23
10CoveredT1,T12,T24
11CoveredT1,T12,T60

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT1,T12,T24
101CoveredT1,T2,T3
110CoveredT1,T60,T61
111CoveredT1,T12,T24

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T12
10CoveredT61,T62,T81

Cond Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_daon_por

SCORECOND
100.00 100.00
tb.dut.u_daon_por_io

SCORECOND
100.00 100.00
tb.dut.u_daon_por_io_div2

SCORECOND
100.00 100.00
tb.dut.u_daon_por_io_div4

SCORECOND
100.00 100.00
tb.dut.u_daon_por_usb

SCORECOND
100.00 100.00
tb.dut.u_daon_lc

SCORECOND
100.00 100.00
tb.dut.u_d0_lc

SCORECOND
100.00 100.00
tb.dut.u_daon_lc_shadowed

SCORECOND
100.00 100.00
tb.dut.u_d0_lc_shadowed

SCORECOND
100.00 100.00
tb.dut.u_daon_lc_aon

SCORECOND
100.00 100.00
tb.dut.u_daon_lc_io

SCORECOND
100.00 100.00
tb.dut.u_d0_lc_io

SCORECOND
100.00 100.00
tb.dut.u_daon_lc_io_div2

SCORECOND
100.00 100.00
tb.dut.u_d0_lc_io_div2

SCORECOND
100.00 100.00
tb.dut.u_daon_lc_usb

SCORECOND
100.00 100.00
tb.dut.u_d0_lc_usb

SCORECOND
100.00 100.00
tb.dut.u_d0_sys

SCORECOND
100.00 100.00
tb.dut.u_daon_sys_io_div4

TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

Branch Coverage for Module : rstmgr_leaf_rst
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T12,T60
0 0 1 Covered T1,T12,T24
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_spi_device
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT60,T25,T61
10CoveredT12,T24,T60
11CoveredT12,T60,T61

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT12,T24,T60
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT12,T24,T60

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T12,T24
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_spi_device
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T12,T60,T61
0 0 1 Covered T12,T24,T60
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_spi_host0
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT1,T8,T60
10CoveredT1,T60,T77
11CoveredT1,T60,T77

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT1,T60,T77
101CoveredT1,T2,T3
110CoveredT1,T60,T61
111CoveredT1,T60,T77

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T60,T77
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_spi_host0
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T60,T77
0 0 1 Covered T1,T60,T77
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_spi_host1
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT8,T23,T60
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_spi_host1
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_usb
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT8,T60,T61
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_usb
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c0
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_i2c0
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT8,T60,T25
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_i2c0
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c1
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_i2c1
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT60,T61,T62
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_i2c1
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c2
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_i2c2
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT8,T60,T25
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10Not Covered

Branch Coverage for Instance : tb.dut.u_d0_i2c2
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

Cond Coverage for Instance : tb.dut.u_daon_por
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_por_io
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_por_usb
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_lc
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc_aon
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc_io
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_lc_io
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_lc_usb
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_lc_usb
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_d0_sys
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable
Line Coverage for Instance : tb.dut.u_d0_usb_aon
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_d0_usb_aon
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------
-1--2-StatusTests
01CoveredT8,T23,T60
10CoveredT60,T61,T62
11CoveredT60,T61,T62

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------
-1--2--3-StatusTests
011CoveredT60,T61,T62
101CoveredT1,T2,T3
110CoveredT60,T61,T62
111CoveredT60,T61,T62

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T61,T62
10CoveredT61,T62,T81

Branch Coverage for Instance : tb.dut.u_d0_usb_aon
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 68 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((sw_rst_req_q && clr_sw_rst_req)) -3-: 72 if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T60,T61,T62
0 0 1 Covered T60,T61,T62
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%